D63GS NEC, D63GS Datasheet - Page 50
D63GS
Manufacturer Part Number
D63GS
Description
Search -----> UPD63GS
Manufacturer
NEC
Datasheet
1.D63GS.pdf
(68 pages)
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AC Characteristics (T
POC Circuit (mask option
50
Command execution time t
K
RESET low-level width
POC-detected voltage
POC circuit current
I
Note 10 + 52/f
Remark t
Notes 1. Operates effectively under the conditions of T
, S
0
, S
Parameter
Parameter
1
high-level width
2. Refers to the voltage with which the POC circuit cancels an internal reset. If V
CY
4 MHz.
reset is released.
From the time of V
period of V
= 64/f
X
Note 2
+ oscillation growth time
X
A
(f
X
= –40 to +85 ˚C, V
POC
Symbol
Symbol
: System clock oscillator frequency)
t
t
V
I
CY
H
RSL
POC
POC
Note 1
V
) (T
POC
DD
V
When releasing
STANDBY mode
lasts less than 1 ms, the internal reset may not take effect.
DD
A
= –20 to +70 ˚C)
V
= 2.2 to 3.6 V
DD
until the internal reset takes effect, lag of up to 1 ms occurs. When the
DD
= 1.8 to 3.6 V)
Test Conditions
Test Conditions
A
= –20 to +70 ˚C, V
at HALT mode
at STOP mode
MIN.
Note
MIN.
DD
15.9
7.9
0.9
10
10
10
= 2.2 to 3.6 V, and f
TYP.
TYP.
1.6
0.9
POC
< V
PD63, 63A, 64
MAX.
MAX.
DD
2.2
1.0
27
27
, the internal
X
= 2.4 to
Unit
Unit
V
A
s
s
s
s
s
s
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