FP31QF ETC, FP31QF Datasheet

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FP31QF

Manufacturer Part Number
FP31QF
Description
2-Watt HFET
Manufacturer
ETC
Datasheet

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FP31QF
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Product Features
Applications
Specifications
1. Pinch-off voltage is measured when I
2. Test conditions unless otherwise noted: T = 25ºC, V
3. 3OIP measured with two tones at an output power of +18 dBm/tone separated by 1 MHz. The
Absolute Maximum Rating
Operation of this device above any of these parameters may cause permanent damage.
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com
DC Parameter
Saturated Drain Current, I
Transconductance, G
Pinch Off Voltage, V
RF Parameter
Operational Bandwidth
Test Frequency
Small Signal Gain
Maximum Stable Gain
Output P1dB
Output IP3
Noise Figure
Parameter
Operating Case Temperature
Storage Temperature
DC Power
RF Input Power (continuous)
Drain to Gate Voltage, V
Junction Temperature
50 – 4000 MHz
18 dB Gain @ 900 MHz
+34 dBm P1dB
+46 dBm Output IP3
High Drain Efficiency
Pb-free 6mm 28-pin QFN package
MTTF > 100 years
Mobile Infrastructure
CATV / DBS
W-LAN / ISM
RFID
Defense / Homeland Security
Fixed Wireless
circuit with Z
suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule.
L
= Z
FP31QF
2-Watt HFET
(3)
LOPT
, Z
S
= Z
(2)
m
p
SOPT
(1)
dss
(optimized for output power).
dg
ds
= 4.8 mA.
Units Min
Units Min
MHz
MHz
dBm
dBm
mA
mS
dB
dB
dB
V
DS
= 9 V, I
Rating
-40 to +85 °C
-55 to +125 °C
7.5 W
6 dB above Input P1dB
+14 V
+220° C
The FP31QF is a high performance 2-Watt HFET
(Heterostructure FET) in a low-cost lead-free 28-pin 6x6
mm QFN (Quad Flatpack, No-Lead) surface-mount
package. This device works optimally at a drain bias of
+9 V and 450 mA to achieve +46 dBm output IP3
performance and an output power of +34 dBm at 1-dB
compression.
The device conforms to WJ Communications’ long
history of producing high reliability and quality
components. The FP31QF has an associated MTTF of a
minimum of 100 years at a mounting temperature of
85°C. All devices are 100% RF & DC tested.
The product is targeted for use as driver amplifiers for
wireless infrastructure where high performance and high
efficiency are required.
DQ
50
= 450 mA, in a tuned application
Product Description
Typ
Typ
1170
590
-2.0
+34
+46
800
3.5
18
24
Max
Max
4000
Typical Performance
4. Typical parameters represent performance in an application circuit.
5. Empirical measurements showed optimal power performance at a drain voltage = 9 volts at 450 mA.
Ordering Information
Parameter
Frequency
Gain
S11
S22
Output P1dB
Output IP3
Noise Figure
IS-95 Channel Power
W-CDMA Ch. Power
Drain Voltage
Drain Current
Part No.
FP31QF
FP31QF-F
FP31QF-PCB900
FP31QF-PCB1900
FP31QF-PCB2140
@ -45 dBc ACPR
@ -45 dBc ACLR
Because the FP31QF is a discrete device, users can choose their own bias configuration. Performance
may vary from the data shown depending on the biasing conditions. To achieve a minimum 1 million
hours MTTF rating, the biasing condition should maintain a junction temperature below 160° C over all
operating temperatures. This can be approximated by (drain voltage) x (drain current) x 17.5° C/W +
(maximum operating temperature).
(3)
(5)
(5)
The Communications Edge
Specifications and information are subject to change without notice
Description
2-Watt HFET
(Leaded QFN Pkg)
2-Watt HFET
(lead-free/RoHS-compliant QFN Pkg)
870 – 960 MHz Application Circuit
1930 – 1990 MHz Application Circuit
2110 – 2170 MHz Application Circuit
Units
MHz
dBm
dBm
dBm
dBm
mA
dB
dB
dB
dB
V
GATE /
Functional Diagram
RF IN
GND
GND
GND
GND
GND
GND
+27.8 +27.3
RF Output
+34
+46
Function
915
RF Input
-20
-12
1
2
3
4
5
6
7
3.5
18
Ground
Drain /
Gate /
Product Information
(4)
28
8
27
+33.8 +33.2 +33.5
+46.8 +46.6 +46.8
9
1960
13.5
-20
-11
4.5
Typical
26
10
450
+9
All other pins &
backside copper
25
11
2140
+25
-18
-24
4.6
13
24
12
Pin No.
19
3
23
13
November 2004
TM
2450
22
14
-18
-15
4.6
12
21
20
19
18
17
16
15
GND
GND
DRAIN /
RF OUT
GND
GND
GND
GND

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FP31QF Summary of contents

Page 1

... DQ Because the FP31QF is a discrete device, users can choose their own bias configuration. Performance may vary from the data shown depending on the biasing conditions. To achieve a minimum 1 million hours MTTF rating, the biasing condition should maintain a junction temperature below 160° C over all operating temperatures. This can be approximated by (drain voltage) x (drain current) x 17.5° ...

Page 2

... FP31QF 2-Watt HFET S-Parameters (V S21, Maximum Stable Gain vs. Frequency DB(|S[2,1]|) DB(MSG 0.5 1 1.5 2 Frequency (GHz) Note: Measurements were made on the packaged device in a test fixture with 50 ohm input and output lines. The S-parameters shown are the de-embedded data down to the device leads and represents typical performance of the device. ...

Page 3

... The C2 and C3 placements are at silk screen markers, “H” and “9.5”, respectively. • The via hole spacing along the main microstrip line is .040”. • The distance from the edge of the FP31QF to the closer edge .305”. • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge ...

Page 4

... FP31QF 2-Watt HFET FP31QF-PCB900 Application Circuit Performance Plots S11 vs. Frequency 0 -40c +25c +85c -5 -10 -15 -20 -25 -30 860 880 900 920 940 Frequency (MHz) P1dB vs. Frequency -40c +25c +85c 26 860 880 900 920 940 Frequency (MHz) OIP3 vs. Temperature ...

Page 5

... The C2 and C3 placements are at silk screen markers, “B” and “3”, respectively. • The via hole spacing along the main microstrip line is .040”. • The distance from the edge of the FP31QF to the closer edge .305”. • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge ...

Page 6

... FP31QF 2-Watt HFET FP31QF-PCB1900 Application Circuit Performance Plots S11 vs. Frequency 0 -40C +25C +85C -5 -10 -15 -20 -25 -30 1930 1950 1970 Frequency (MHz) P1dB vs. Frequency -40c +25c +85c 26 1930 1950 1970 Frequency (MHz) OIP3 vs. Temperature freq = 1960, 1961 MHz ...

Page 7

... The C2 and C3 placements are at silk screen markers, “A” and “2.5”, respectively. • The via hole spacing along the main microstrip line is .040”. • The distance from the edge of the FP31QF to the closer edge .305”. • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge ...

Page 8

... FP31QF 2-Watt HFET FP31QF-PCB2140 Application Circuit Performance Plots S11 vs. Frequency 0 -40c +25c +85c -5 -10 -15 -20 -25 -30 2110 2130 2150 2170 Frequency (MHz) P1dB vs. Frequency -40C +25C +85C 26 2110 2130 2150 2170 Frequency (MHz) OIP3 vs. Temperature freq = 2140, 2141 MHz ...

Page 9

... The C2 and C3 placements are at silk screen markers, “A” and “2”, respectively. • The via hole spacing along the main microstrip line is .040”. • The distance from the edge of the FP31QF to the closer edge .305”. • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge ...

Page 10

... The via hole spacing along the main microstrip line is .040”. • The distance from the edge of the FP31QF to the closer edge .305”. • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge ...

Page 11

... The active-bias circuit, shown on the right, uses dual PNP transistors to provide a constant drain current into the FP31QF, while also eliminating the effects of pinchoff variation. This configuration is best suited for applications where the intended output power level of the amplifier is backed off at least 6 dB away from its compression point ...

Page 12

... FP31QF 2-Watt HFET FP31QF Mechanical Information This package may contain lead-bearing materials. The plating material on the pins is SnPb. Outline Drawing Mounting Configuration / Land Pattern Thermal Specifications Parameter Rating Operating Case Temperature -40 to +85°C (1) Thermal Resistance, Rth 17.5° C/W (2) Junction Temperature, Tjc 156° ...

Page 13

... FP31QF 2-Watt HFET FP31QF-F Mechanical Information This package is lead-free/RoHS-compliant compatible with both lead-free (maximum 260°C reflow temperature) and leaded (maximum 245°C reflow temperature) soldering processes. The plating material on the pins is annealed matte tin over copper. Outline Drawing Mounting Configuration / Land Pattern ...

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