74HCT175PW,112 NXP Semiconductors, 74HCT175PW,112 Datasheet - Page 10
![IC QUAD D F-F POS-EDGE 16-TSSOP](/photos/6/56/65607/568-16-tssop_sot403-1_sml.jpg)
74HCT175PW,112
Manufacturer Part Number
74HCT175PW,112
Description
IC QUAD D F-F POS-EDGE 16-TSSOP
Manufacturer
NXP Semiconductors
Series
74HCTr
Type
D-Type Busr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HCT175D652.pdf
(13 pages)
Specifications of 74HCT175PW,112
Function
Master Reset
Output Type
Differential
Number Of Elements
1
Number Of Bits Per Element
4
Frequency - Clock
49MHz
Delay Time - Propagation
19ns
Trigger Type
Positive Edge
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Other names
568-2798-5
935188970112
935188970112
Philips Semiconductors
HC TYPES
AC waveforms 74HC
AC waveforms 74HC
March 1988
handbook, full pagewidth
HCMOS family characteristics
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET
(2) For AC measurements: t
Fig.4
and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals
are specified in the individual device data sheet.
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
OUTPUT
PRESET
CLOCK
RESET,
INPUT
INPUT
INPUT
r
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
INPUT
OUTPUT
10 %
50%
t su
t rem
50%
t r
10%
50%
t PLH
90%
t PHL
t THL
t WH
10%
max
90%
50%
90%
t h
, there is no constraint on t
t r
1/f max
t TLH
50%
90%
t f
50%
10%
10
t WL
t su
t f
t PHL
t PLH
t TLH
r
, t
f
with 50% duty factor.
MGK564
t h
FAMILY SPECIFICATIONS
t THL
V CC
GND
MGK569
V CC
GND
V CC
GND
V CC
GND