74LVC1G79GW,125 NXP Semiconductors, 74LVC1G79GW,125 Datasheet - Page 15

• Manufacturer Part Number: 74LVC1G79GW,125
• Description: IC SGL D FF POS-EDG TRIG 5-TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Typer

Specifications of 74LVC1G79GW,125

• Output Type: Non-Inverted
• Package / Case: SC-70-5, SC-88A, SOT-323-5, SOT-353, 5-TSSOP
• Function: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 500MHz
• Delay Time - Propagation: 1.7ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: LVC
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 2.2 ns at 3.3 V
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.65 V
• Technology: CMOS
• Number Of Bits: 1
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: SOT
• Frequency (max): 200MHz
• Operating Supply Voltage (min): 1.65V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4838-2; 74LVC1G79GW,125; 74LVC1G79GW-G; 74LVC1G79GW-G; 935268675125

NXP Semiconductors
Fig 14. Package outline SOT1115 (XSON6)
74LVC1G79
Product data sheet
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
mm
SOT1115
Unit
Outline
version
max
nom
min
0.35 0.04
A
(1)
A
1
0.20
0.15
0.12
b
IEC
0.95
0.90
0.85
terminal 1
index area
D
e
(6×)
1.05
1.00
0.95
L
(2)
E
1
0.55
JEDEC
e
All information provided in this document is subject to legal disclaimers.
1
6
0.3
e
e
1
1
References
Rev. 8 — 30 September 2010
D
2
5
0.35
0.30
0.27
0
L
e
1
0.40
0.35
0.32
L
b
3
4
1
JEITA
scale
0.5
A
L
E
1
A
Single D-type flip-flop; positive-edge trigger
1 mm
(4×)
(2)
European
projection
74LVC1G79
© NXP B.V. 2010. All rights reserved.
Issue date
10-04-02
10-04-07
sot1115_po
SOT1115
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