NT256D64S88B1G Nanya Technology, NT256D64S88B1G Datasheet - Page 4

• Manufacturer Part Number: NT256D64S88B1G
• Description: (NT256D64S88Bxx) 256MB DDR DIMM
• Manufacturer: Nanya Technology

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Input/Output Functional Description
REV 2.2
Aug 3, 2004
Preliminary
CK0, CK1, CK2,
DQS9 – DQS16
RAS, CAS, WE
DQS0 - DQS7,
CK0, CK1, CK2
CKE0, CKE1
DQ0 - DQ63
DM0 – DM8
CB0 – CB7
SA0 – SA2
BA0, BA1
A11, A12
V
A10/AP
Symbol
A0 - A9
V
S0, S1
DD
V
SDA
V
SCL
DDSPD
DDQ
REF
, V
SS
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Supply
Supply
Supply
Supply
Input
Type
Polarity
Active
Active
Active
Active
Active
Cross
point
High
High
High
Low
Low
-
-
-
-
-
-
-
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is
selected by S1.
When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to
be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high.
In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is
not used on x64 modules.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either V
Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pull-up.
Serial EEPROM positive power supply.
4
NANYA reserves the right to change products and specifications without notice.
DD
or V
Function
SS
on the system board to configure the Serial
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