RM5231A-350-H PMC-Sierra Inc, RM5231A-350-H Datasheet - Page 21

• Manufacturer Part Number: RM5231A-350-H
• Description: RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
3.19 Data Cache
Since the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel
with the cache access, further increasing performance by allowing these two operations to occur
simultaneously. The cache tag contains a 24-bit physical address, a valid bit, and has a single
parity bit.
The instruction cache is 64-bits wide and can be accessed each processor cycle. Accessing 64 bits
per cycle allows the instruction cache to supply two instructions per cycle to the superscalar
dispatch unit. For typical code sequences where a floating-point load or store and a floating-point
computation instruction are being issued together in a loop, the entire bandwidth available from
the instruction cache is consumed.
Cache miss refill writes 64 bits per cycle to minimize the cache miss penalty. The line size is eight
instructions (32 bytes) to maximize the performance of communication between the processor and
the memory system.
The RM5231A supports instruction cache locking. The contents of one set of the cache, set A, can
be locked by setting a bit in the coprocessor 0 Status register. Locking the set prevents its contents
from being overwritten by a subsequent cache miss. A refill occurs only into set B. This
mechanism allows the programmer to lock critical code into the cache thereby guaranteeing
deterministic behavior for the locked code sequence.
For fast, single cycle data access, the RM5231A includes a 32KB on-chip data cache that is two-
way set associative with a fixed 32-byte (eight words) line size.
The data cache is protected with byte parity and its tag is protected with a single parity bit. It is
virtually indexed and physically tagged to allow simultaneous address translation and data cache
access.
Cache protocols supported for the data cache are:
1. Uncached
2. Write-back
3. Write-through with write allocate
Data loads and instruction fetches from uncached memory space are brought in from main
memory to the register file and the execution unit, respectfully. The caches are not accessed.
Data stores to uncached memory space go directly to the main memory without updating the
data cache.
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated, and the
cache line is marked for later write-back. If the cache lookup misses, the target cache line is
first brought into the cache and then the write is performed as above.
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
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