MBM29DL32TF Fujitsu, MBM29DL32TF Datasheet - Page 29

• Manufacturer Part Number: MBM29DL32TF
• Description: 32M-Bit Dual Operation Flash Memory
• Manufacturer: Fujitsu

28
MBM29DL32TF/BF
9. Temporary Sector Group Unprotection
10. RESET
11. Byte/Word Configuration
12. Boot Block Sector Protection
CHART for sector group protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force V
with CE and OE at V
and A
sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses,
except for A
manufacturer and device codes. A
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02h, where the higher order addresses (A
A
sector group. See “MBM29DL32TF/BF Sector Group Protection Verify Autoselect Codes Tables” and
“MBM29DL32TF/BF Extended Autoselect Code Tables” in DEVICE BUS OPERATION for Autoselect codes.
This feature allows temporary unprotection of previously protected sector groups of the MBM29DL32TF/BF
devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to
high voltage (V
the sector group addresses. Once the V
groups will be protected again. Refer to “16. Temporary Sector Group Unprotection Timing Diagram” in TIMING
DIAGRAM and “6. Temporary Sector Group Unprotection Algorithm” in FLOW CHART.
The MBM29DL32TF/BF devices may be reset by driving the RESET pin to V
requirement and has to be kept low (V
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode “t
devices require an additional “t
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See “11. RESET, RY/BY Timing
Diagram” in TIMING DIAGRAM for the timing diagram. Refer to “9. Temporary Sector Group Unprotection” for
additional functionality.
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32TF/BF devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to “12. Timing Diagram for Word Mode Configuration”, “13. Timing Diagram for Byte Mode Configuration” and
“14. BYTE Timing Diagram for Write Operations” in TIMING DIAGRAM for the timing diagram.
The Write Protection function provides a hardware method of protecting certain boot sectors without using V
This function is one of two provided by the WP/ACC pin.
If the system asserts V
“outermost” 8 K byte boot sectors (MBM29DL32TF : SA69 and SA70, MBM29DL32BF : SA0 and SA1) inde-
pendently of whether those sectors were protected or unprotected using the method described in “Sector Group
Protection”. The two outermost 8 K byte boot sectors are the two sectors containing the lowest addresses in a
Hardware Reset
17
, A
16
12
15
) while (A
, A
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
15
, A
6
, A
14
ID
, A
) . During this mode, formerly protected sector groups can be programmed or erased by selecting
6
1
, A
, and A
13
READY
, and A
3
, A
IL
and WE at V
2
, A
” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
IL
0
on the WP/ACC pin, the device disables program and erase functions in the two
1
12
are DON’T CARES. Address locations with A
, A
) are the desired sector group address will produce a logic “1” at DQ
0
)
RH
” before it will allow read access. When the RESET pin is low, the devices will
-1
(0, 0, 0, 1, 0) will produce a logic “1” code at device output DQ
IH
requires to apply to V
. Scanning the sector group addresses (A
-70
IL
ID
14
) for at least “t
is taken away from the RESET pin, all the previously protected sector
to DQ
8
bits are tri-stated. However, the command bus cycle is always
RP
” in order to properly reset the internal state machine.
IL
7
on byte mode.
to DQ
0
and the DQ
1
20
V
15
IL
, A
IL
. The RESET pin has a pulse
to DQ
are reserved for Autoselect
19
, A
8
18
bits are ignored. Refer
, A
ID
17
on address pin A
, A
0
0
16
for a protected
for a protected
, A
20
15
, A
, A
15
/A
19
14
, A
, A
-1
pin
13
18
ID
9
0
,
,
.