MBM29SL800BE Fujitsu Media Devices, MBM29SL800BE Datasheet - Page 22

• Manufacturer Part Number: MBM29SL800BE
• Description: (MBM29SL800TE/BE) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT
• Manufacturer: Fujitsu Media Devices

22
MBM29SL800TE/BE
RY/BY
Ready/Busy
Byte/Word Configuration
Data Protection
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
Sector Protection
The MBM29SL800TE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any
read/write or erase operation. If the MBM29SL800TE/BE are placed in an Erase Suspend mode, the RY/BY
output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operation
Timing Diagram” and “RESET, RY/BY Timing Diagram” in
The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to V
be connected to the host system via more than one RY/BY pin in parallel.
The BYTE pin selects the Byte (8-bit) mode or Word (16-bit) mode for the MBM29SL800TE/BE devices. When
this pin is driven high, the devices operate in the Word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
The MBM29SL800TE/BE are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices automat-
ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of
the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE
must be a logical zero while OE is a logical one.
Power-up of the devices with WE
The internal state machine is automatically reset to the read mode on power-up.
Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
program and erase commands that are addressed to protected sectors. Any commands to program or erase
addressed to ptotected sector are ignored. (See “Sector Ptotection” in “
0
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
CE
14
V
-90/10
to DQ
IL
and OE
V
8
bits are tri-stated. However, the command bus cycle is always
IL
, CE
V
IH
V
will not accept commands on the rising edge of WE.
7
IH
to DQ
, or WE
TIMING DIAGRAM for a detailed timing diagram.
0
and the DQ
V
IH
. To initiate a write cycle CE and WE
FUNCTIONAL DESCRIPTION”.)
15
to DQ
CC
; multiples of devices may
8
bits are ignored.
CC
power-up
15
/A-
1
pin
15