ds26504 Maxim Integrated Products, Inc., ds26504 Datasheet - Page 83

• Manufacturer Part Number: ds26504
• Description: Ds26504 T1/e1/j1/64kcc Bits Element
• Manufacturer: Maxim Integrated Products, Inc.

DS26504 T1/E1/J1/64KCC BITS Element
clock/data recovery block or the clock applied at the TCLK pin is adjusted to create a smooth jitter-free
clock that is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a
gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming
jitter exceeds either 120UI
(buffer depth is 128 bits) or 28UI
(buffer depth is 32 bits), then the
P-P
P-P
DS26504 will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17
instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17,
it also sets the Jitter Attenuator Limit Trip (JALT) bit in Status Register 1 (SR1.4).
13.6 CMI (Code Mark Inversion) Option
The DS26504 provides a CMI interface for connection to optical transports. This interface is a unipolar
1T2B type of signal. Ones are encoded as either a logical one or zero level for the full duration of the
clock period. Zeros are encoded as a zero-to-one transition at the middle of the clock period.
Figure 13-3. CMI Coding
CLOCK
1
1
0
1
0
0
1
DATA
CMI
Transmit and receive CMI is enabled via LIC4.7. When this register bit is set, the TTIP pin outputs CMI-
coded data at normal levels. This signal can be used to directly drive an optical interface. When CMI is
enabled, the user can also use HDB3/B8ZS coding. When this register bit is set, the RTIP pin becomes a
unipolar CMI input. The CMI signal is processed to extract and align the clock with data.
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