ds26504 Maxim Integrated Products, Inc., ds26504 Datasheet - Page 84

• Manufacturer Part Number: ds26504
• Description: Ds26504 T1/e1/j1/64kcc Bits Element
• Manufacturer: Maxim Integrated Products, Inc.

13.7 LIU Control Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: Transmit Power-Down (TPD)
Bit 1: Disable Jitter Attenuator (DJA)
Bit 2/Jitter Attenuator Buffer Depth Select (JABDS)
Bit 3: Jitter Attenuator Select (JAS)
Bit 4: Receive Equalizer Gain Limit (EGL). This bit controls the sensitivity of the receive equalizer.
Bits 5, 6, 7: Line Build-Out Select (L0 to L2). When using the internal termination, the user needs only to select 000 for 75Ω
operation or 001 for 120Ω operation. This selects the proper voltage levels for 75Ω or 120Ω operation. Using TT0, TT1, and
TT2 of the LICR4 register, users can then select the proper internal source termination. Line build-outs 100 and 101 are for
backwards compatibility with older products only.
E1 Mode
N.M. = Not meaningful
Note 1: Transformer turns ratio.
Note 2: TT0, TT1, and TT2 of the LIC4 register must be set to zero in this configuration.
L2
0
0
1
1
L1
0
0
0
0
0 = powers down the transmitter and three-states the TTIP and TRING pins
1 = normal transmitter operation
0 = jitter attenuator enabled
1 = jitter attenuator disabled
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
T1 Mode: 0 = -36dB (long haul)
E1 Mode: 0 = -43dB (long haul)
L0
PIN 13
0
1
0
1
L2
L2
7
0
75Ω normal
120Ω normal
75Ω with high return loss (Note 2)
120Ω with high return loss (Note 2)
1 = -15dB (limited long haul)
1 = -12dB (short haul)
PIN 12
L1
L1
LIC1
Line Interface Control 1
30h
6
0
APPLICATION
PIN 11
L0
L0
5
0
EGL
4
0
0
84 of 128
N (Note 1)
1:2
1:2
1:2
1:2
JAS
3
0
0
JABDS
RETURN LOSS
2
0
0
21dB
21dB
N.M.
N.M.
DS26504 T1/E1/J1/64KCC BITS Element
DJA
1
0
0
Rt (Note 1)
11.6Ω
6.2Ω
TPD
0
0
0
0
1