upd161608 Renesas Electronics Corporation., upd161608 Datasheet - Page 13

• Manufacturer Part Number: upd161608
• Description: 176-rgb X 220-dot 1-chip Driver Ic For 262,144-color Tft-lcd Display
• Manufacturer: Renesas Electronics Corporation.

<R>
<R>
<R>
3.2 Interface Pins
RL
TB
BGR
REV
SHUT
CM
CSB
SCK
SDI
SDO
SPID
DOTCLK
ENABLE
CAD
TMB
Symbol
189, 190
186, 187
183, 184
180, 181
192 to 194
262 to 264
161 to 163
159, 160
157, 158
155, 156
171, 172
195 to 197
204 to 206
177, 178
126
Pad No.
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
This pin’s setting is valid. Source output direction is controlled as follows.
- Connect to V
- Connect to V
Input pin to select the Gate driver scan direction.
- Connect to V
- Connect to V
Input pin to select the color mapping.
- Connect to V
- Connect to V
Input pin to select the display reversion.
- Connect to V
- Connect to V
This pin’s setting is valid. Power circuit Shut down is controlled as follows.
High level: Shut down (power off, Standby sequence)
Low level: Display on sequence (power circuit start operation sequentially)
Input pin to select 262 K-color or 8-color display mode. After entered 8-color display mode,
only MSB of the data Red, Green and Blue will be considered.
High level: 8-color display mode
Low level: 262 K-color display mode
When set to 8-color mode, S0-S527 output VCIX2 voltage and V
Chip Select input pin.
High level:
Low level:
When not used this pin, leave it open.
Serial clock input pin for a clock-synchronous serial interface.
When not used this pin, leave it open. This pin is also pulled up inside IC.
Serial data input pin for a clock-synchronous serial interface. The input data is latched by
the rising edge of SCK signal. When not used this pin, leave it open.
This pin is also pulled up inside IC.
Serial data Output pin for a clock-synchronous serial interface. The data is output at the
falling edge of SCK signal. When not used this pin, leave it open.
ID selection pin for the SPI serial interface. When sending serial data, the “ID” bit must
much with the logic stage of this pin.
High level: ID = 1
Low level: ID = 0
Dot clock signal for RGB interface. A non-stop external clock must be provided to that pin
even at front or back porch non-display period.
Display data are fetched at rising edge of DOTCLK
Data enabling signal for using RGB interface.
High level: Valid (possible to access), it qualifies the valid are of display data input.
Low level: Invalid (not possible to access)
Although it is intact, since potential fixation is required, give as low fixation.
Gamma initial value setting pin.
High level: Mode 1
Low level: Mode2
This pin is pulled up internally IC. So if this pin leave open, Mode1 is selected.
Data Sheet S17594EJ2V0DS
μ
μ
PD161608 is selected and can be accessed.
PD161608 is not selected and cannot be accessed.
DDIO
SS
DDIO
SS
DDIO
SS
DDIO
SS
: S527 → S0 source driving mode.
for Gate scan from G219 to G0
for Red-Green-Blue mapping
for mapping data “0” to minimum pixel voltage for normally black panel
: S0 → S527 source driving mode.
for Gate scan from G0 to G219
for Blue-Green-Red mapping
for mapping data “0” to maximum pixel voltage for normally white panel
Description
SS
levels for LCD driving.
μ
PD161608
(1/2)
13