upd161608 Renesas Electronics Corporation., upd161608 Datasheet - Page 39

• Manufacturer Part Number: upd161608
• Description: 176-rgb X 220-dot 1-chip Driver Ic For 262,144-color Tft-lcd Display
• Manufacturer: Renesas Electronics Corporation.

13.6 Frame Cycle Control (R0BH)
NO1, NO0: Set the gate non-overlap period.
SDT1, SDT0: Specify the timing on which a source signal is output after falling edge of a gate signal.
EQ1, EQ0: Equalized period is added as specified by bits of EQ1-EQ0. The equalization signal is output for scan line.
PT1, PT0: Set the division ratio of clocks for internal operation. Internal operations are driven by clocks which frequency
R/W
W
are divided according to the PT1, PT0 setting.
RS
1
Remark Clock cycle: DOTCLK cycle
Remark f
Note In power up sequence, only when being setup before starting SHUT pin, the setup of this
Remark Clock cycle: DOTCLK cycle
Remark Clock cycle: DOTCLK cycle
NO1
IB15 IB14 IB13 IB12 IB11 IB10
SDT1
NO1
EQ1
PT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
command is valid.
NO0
OSC
SDT1 SDT0
= DOTCLK frequency
SDT0
PT0
NO0
EQ0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EQ1
Data Sheet S17594EJ2V0DS
EQ0
PT1
IB9
Delay amount of the source output
Internal Operation clock frequency
IB8
PT0
Gate non-overlap Period
A:B ratio = 1:7
Equalizing Period
4 clock cycle
4 clock cycle
4 clock cycle
4 clock cycle
18 clock cycle
26 clock cycle
Not equalized
IB7
0 clock cycle
4 clock cycle
6 clock cycle
8 clock cycle
Reserved
Reserved
Reserved
0
f
OSC
/1
IB6
0
Note
IB5
0
IB4
0
IB3
0
IB2
0
μ
PD161608
IB1
0
IB0
0
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