upd72872 Renesas Electronics Corporation., upd72872 Datasheet - Page 20

no-image

upd72872

Manufacturer Part Number
upd72872
Description
Ieee1394 1-chip Ohci Host Controller
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
upd72872GC
Manufacturer:
PHI
Quantity:
1 019
Part Number:
upd72872GC-9EV
Manufacturer:
NEC
Quantity:
20 000
3.1.1 Offset_00
3.1.2 Offset_02
3.1.3 Offset_04
20
15-0
15-0
0
1
2
3
4
5
6
7
8
9
15-10
This register identifies the manufacturer of the µ PD72872. The ID is assigned by the PCI_SIG committee.
This register identifies the type of the device for the µ PD72872. The ID is assigned by NEC Corporation.
The register provides control over the device’s ability to generate and respond to PCI cycles.
Bits
Bits
Bits
Vendor ID Register
Device ID Register
Command Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Constant value of 1033H.
Constant value of 00CEH.
I/O enable Constant value of 0. The µ PD72872 does not respond to PCI I/O accesses.
Memory enable Default value of 1. It defines if the µ PD72872 responds to PCI memory
accesses. This bit should be set to one upon power-up reset.
Master enable Default value of 1. It enables the µ PD72872 as bus-master on the PCI-bus.
Special cycle monitor enable Constant value of 0. The special cycle monitor is always
disabled.
Memory write and invalidate enable Default value of 1. It enables Memory Write and Invalid
Command generation.
VGA color palette invalidate enable Constant value of 0. VGA color palette invalidate is
always disabled.
Parity error response Default value of 0. It defines if the µ PD72872 responds to PERR.
Stepping enable Constant value of 0. Stepping is always disabled.
System error enable Default value of 0. It defines if the µ PD72872 responds to SERR.
Fast back-to-back enable Constant value of 0. Fast back-to-back transactions are only
allowed to the same agent.
Reserved Constant value of 000000.
0: The µ PD72872 does not respond to PCI memory cycles
1: The µ PD72872 responds to PCI memory cycles
0: The µ PD72872 cannot generate PCI accesses by being a bus-master
1: The µ PD72872 is capable of acting as a bus-master
0: Memory write must be used
1: The µ PD72872, when acts as PCI master, can generate the command
0: Ignore parity error
1: Respond to parity error
0: Disable system error checking
1: Enable system error checking
Data Sheet S14793EJ1V0DS
Description
Description
Description

Related parts for upd72872