upd72872 Renesas Electronics Corporation., upd72872 Datasheet - Page 31

• Manufacturer Part Number: upd72872
• Description: Ieee1394 1-chip Ohci Host Controller
• Manufacturer: Renesas Electronics Corporation.

4.1.2 Cable Interface Circuit
encoded, converted from parallel to serial and transmitted.
after synchronization by SCLK
of 100/200/400 Mbps.
the 1394 bus is transmitted to the state machine in the LSI.
4.1.3 CPS
If the cable power falls under 7.5 V there is an indication to the Link layer that the power has failed.
4.1.4 Unused Ports
4.2 PLL and Crystal Oscillation Circuit
4.2.1 Crystal Oscillation Circuit
4.2.2 PLL
4.3 PC0-PC2
Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can be
changed with software through the Link layer; this pin sets the initial value during Power-on Reset. Use a pull-up or
pull-down resistor of 10 kΩ based on the application.
4.4 P_RESETB
reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register.
4.5 RI0, RI1
Note The SCLK is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal signal in the
Each port is configured with two twisted-pairs of TpA and TpB.
TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables.
During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is
While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel
The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of
An external resistance of 390 kΩ is connected in series to the power cable to monitor the power of the power cable.
TpAp, TpAn : Not connected
TpBp, TpBn : AGND
TpBias
To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm.
The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).
The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to
Connect an external capacitor of 0.1 µ F between the pins P_RESETB and GND. If the voltage drops below 0 V, a
Connect an external resistor of 9.1 kΩ ± 0.5 % to limit the LSI’s current.
µ PD72872.
: Not connected
Note
, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate
Data Sheet S14793EJ1V0DS
31