74AHCT1G79GV,125 NXP Semiconductors, 74AHCT1G79GV,125 Datasheet
![IC D F-F POS-EDGE TRIG SC74A-5](/photos/6/96/69695/sot753_sml.jpg)
74AHCT1G79GV,125
Specifications of 74AHCT1G79GV,125
74AHCT1G79GV
935271671125
Related parts for 74AHCT1G79GV,125
74AHCT1G79GV,125 Summary of contents
Page 1
Single D-type flip-flop; positive-edge trigger Rev. 05 — 2 July 2007 1. General description 74AHC1G79 and 74AHCT1G79 are high-speed Si-gate CMOS devices. They provide a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to ...
Page 2
... NXP Semiconductors 4. Marking Table 2. Marking codes Type number 74AHC1G79GW 74AHC1G79GV 74AHCT1G79GW 74AHCT1G79GV 5. Functional diagram mna440 Fig 1. Logic symbol CP D Fig 3. Logic diagram 74AHC_AHCT1G79_5 Product data sheet 74AHC1G79; 74AHCT1G79 Marking AP A79 CP C79 Q 4 Fig 2. IEC logic symbol Rev. 05 — 2 July 2007 Single D-type flip-flop; positive-edge trigger ...
Page 3
... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin GND Functional description [1] Table 4. Function table Inputs HIGH voltage level LOW voltage level; = LOW-to-HIGH CP transition don’t care state after the next LOW-to-HIGH CP transition. ...
Page 4
... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I I input clamping current IK I output clamping current OK I output current O I supply current ...
Page 5
... NXP Semiconductors Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level output voltage 4.0 mA 8.0 mA LOW-level output voltage 4.0 mA 8.0 mA input leakage GND current 5 supply current 5 input I capacitance For type 74AHCT1G79 V HIGH-level input voltage V LOW-level ...
Page 6
... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 3.0 ns. For test circuit see r f Symbol Parameter Conditions For type 74AHC1G79 t propagation delay set-up time hold time pulse width clock HIGH or LOW W f maximum max frequency C power per buffer; PD dissipation ...
Page 7
... NXP Semiconductors 12. Waveforms D input CP input Q output Measurement points are given in V and V are typical output voltage levels that occur with the output Fig 5. Clock (CP) to output (Q) propagation delay times, clock pulse width set-up times, the hold times and maximum clock pulse frequency Table 9 ...
Page 8
... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION IEC SOT353-1 Fig 7 ...
Page 9
... NXP Semiconductors Plastic surface-mounted package; 5 leads DIMENSIONS (mm are the original dimensions UNIT 0.100 0.40 1.1 0.26 mm 0.013 0.25 0.9 0.10 OUTLINE VERSION IEC SOT753 Fig 8. Package outline SOT753 (SC-74A) 74AHC_AHCT1G79_5 Product data sheet 74AHC1G79; 74AHCT1G79 scale 3.1 1.7 3.0 0.6 0.95 2 ...
Page 10
... Release date 74AHC_AHCT1G79_5 20070702 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Package SOT353 changed to SOT353-1 in • ...
Page 11
... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
Page 12
... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 14 Abbreviations ...