74AHCT374PW,112 NXP Semiconductors, 74AHCT374PW,112 Datasheet
74AHCT374PW,112
Specifications of 74AHCT374PW,112
74AHCT374PW
935262683112
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74AHCT374PW,112 Summary of contents
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Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 03 — 12 June 2008 1. General description The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AHC374 74AHC374D +125 C 74AHC374PW +125 C 74AHCT374 74AHCT374D +125 C 74AHCT374PW +125 C 4. Functional diagram Fig 1. Functional diagram 74AHC_AHCT374_3 Product data sheet 74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state ...
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... NXP Semiconductors Fig 2. Logic symbol FF1 FF2 Fig 4. Logic diagram 74AHC_AHCT374_3 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state mna891 Fig FF3 FF4 Rev. 03 — 12 June 2008 74AHC374; 74AHCT374 mna196 IEC logic symbol FF5 FF6 FF7 FF8 Q6 Q7 mna893 © ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SO20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin GND 74AHC_AHCT374_3 Product data sheet 74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state 374 GND 10 001aad040 Description 3-state output enable input (active LOW) 3-state fl ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Load and read register Load register and disable outputs [ HIGH voltage level HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition LOW voltage level LOW voltage level one setup time prior to the LOW-to-HIGH CP transition; ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter 74AHC374 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74AHCT374 V supply voltage CC V input voltage I V output voltage O T ambient temperature ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 OFF-state output current 5 supply current 5 input capacitance C output O capacitance 74AHCT374 V HIGH-level input voltage V LOW-level input voltage V HIGH-level ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC374 t propagation CP to Qn; see pd delay Figure enable time OE to Qn; see disable time OE to Qn; see dis 3.6 V ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t hold time Dn to CP; see power MHz dissipation capacitance 74AHCT374 4 5 propagation CP to Qn; see pd delay Figure enable time OE to Qn; see disable time OE to Qn; see ...
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... NXP Semiconductors 10.1 Waveforms CP input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Clock pulse width, maximum frequency and input to output propagation delays OE input Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH ...
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... NXP Semiconductors CP input Dn input Qn output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical voltage output levels that occur with the output load Fig 8. Data set-up and hold times Table 8. ...
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... NXP Semiconductors negative positive Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance load resistance test selection switch. Fig 9. Test circuitry for measuring switching times Table 9. Test data Type Input ...
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... NXP Semiconductors 11. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... Document ID Release date 74AHC_AHCT374_3 20080612 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74AHC_AHCT374_2 19990928 74AHC_AHCT374_1 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 13 Revision history ...