74AHCT126PW,112 NXP Semiconductors, 74AHCT126PW,112 Datasheet

IC BUFF DVR TRI-ST QD 14TSSOP

74AHCT126PW,112

Manufacturer Part Number
74AHCT126PW,112
Description
IC BUFF DVR TRI-ST QD 14TSSOP
Manufacturer
NXP Semiconductors
Series
74AHCTr
Datasheet

Specifications of 74AHCT126PW,112

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
8mA, 8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Logic Family
AHCT
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
4 / 4
Output Type
3-State
Propagation Delay Time
7.5 ns at 4.5 V to 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74AHCT126PW
74AHCT126PW
935262767112
1. General description
2. Features
The 74AHC126; 74AHCT126 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC126; 74AHCT126 provides four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE).
A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC126; 74AHCT126 is identical to the 74AHC125; 74AHCT125 but has active
HIGH output enable inputs.
I
I
I
I
I
I
I
74AHC126; 74AHCT126
Quad buffer/line driver; 3-state
Rev. 03 — 25 April 2008
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
Input levels:
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
N
N
N
N
N
For 74AHC126: CMOS level
For 74AHCT126: TTL level
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
CC
Product data sheet

Related parts for 74AHCT126PW,112

74AHCT126PW,112 Summary of contents

Page 1

Quad buffer/line driver; 3-state Rev. 03 — 25 April 2008 1. General description The 74AHC126; 74AHCT126 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance with JEDEC ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC126 74AHC126D +125 C 74AHC126PW +125 C 74AHCT126 74AHCT126D +125 C 74AHCT126PW +125 C 4. Functional diagram Fig 1. Functional diagram nA nOE Fig 2. Logic symbol 74AHC_AHCT126_3 Product data sheet 74AHC126; 74AHCT126 Description SO14 plastic small outline package ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 4. Pin configuration SO14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin 1OE 2OE GND 3OE 4OE 74AHC_AHCT126_3 Product data sheet 74AHC126; 74AHCT126 1OE 126 2OE GND 7 8 001aac982 Description output enable input 1 (active HIGH) ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Control nOE [ HIGH voltage state LOW voltage state don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter 74AHC126 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74AHCT126 V supply voltage CC V input voltage I V output voltage O T ambient temperature ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 OFF-state output current 5 supply current 5 input capacitance C output O capacitance 74AHCT126 V HIGH-level input voltage V LOW-level input voltage V HIGH-level ...

Page 7

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC126 t propagation nA to nY; see pd delay enable time nOE to nY; see disable time nOE to nY; see dis 3.6 V ...

Page 8

... NXP Semiconductors [1] Typical values are measured at nominal supply voltage (V [ the same as t and PLH PHL [ the same as t and PZL PZH [ the same as t and t . dis PLZ PHZ [ used to determine the dynamic power dissipation ( input frequency in MHz output frequency in MHz output load capacitance in pF; ...

Page 9

... NXP Semiconductors Table 8. Measurement points Type Input V M 74AHC126 0.5 74AHCT126 1.5 V negative positive Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance load resistance test selection switch. Fig 7. Test circuitry for measuring switching times Table 9 ...

Page 10

... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... Document ID Release date 74AHC_AHCT126_3 20080425 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74AHC_AHCT126_2 19990929 74AHC_AHCT126_N_1 ...

Page 13

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 14

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history ...

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