74HC173D,653 NXP Semiconductors, 74HC173D,653 Datasheet - Page 6
![IC QUAD D F-F POS-EDGE 16SOIC](/photos/6/52/65286/16-soic_sot109-1_sml.jpg)
74HC173D,653
Manufacturer Part Number
74HC173D,653
Description
IC QUAD D F-F POS-EDGE 16SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Type
D-Type Busr
Datasheet
1.74HCT173DB112.pdf
(10 pages)
Specifications of 74HC173D,653
Output Type
Tri-State Non Inverted
Package / Case
16-SOIC (3.9mm Width)
Function
Master Reset
Number Of Elements
1
Number Of Bits Per Element
4
Frequency - Clock
95MHz
Delay Time - Propagation
16ns
Trigger Type
Positive Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
HC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
17 ns at 5 V
High Level Output Current
- 7.8 mA
Low Level Output Current
7.8 mA
Supply Voltage (max)
6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
2 V
Technology
CMOS
Number Of Bits
4
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Operating Supply Voltage (typ)
5V
Package Type
SO
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
6V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4558-2
74HC173D-T
74HC173D-T
933714560653
74HC173D-T
74HC173D-T
933714560653
Philips Semiconductors
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
Output capability: bus driver
I
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
December 1990
CC
t
t
t
t
t
t
t
t
t
t
SYMBOL
PHL
PHL
PZH
PHZ
THL
W
W
rem
su
su
Quad D-type flip-flop; positive-edge trigger; 3-state
category: MSI
/ t
/ t
/ t
/ t
TLH
PLH
PZL
PLZ
propagation delay
propagation delay
3-state output enable time
3-state output disable time
output transition time
clock pulse width
master reset pulse
removal time
set-up time
set-up time
r
= t
CP to Q
MR to Q
OE
OE
HIGH or LOW
width; HIGH
MR to CP
E
D
n
n
f
to CP
to CP
= 6 ns; C
n
n
PARAMETER
to Q
to Q
n
n
n
n
L
= 50 pF
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
80
16
14
80
16
14
60
12
10
100
20
17
60
12
10
min. typ. max. min. max. min. max.
55
20
16
44
16
13
52
19
15
52
19
15
14
5
4
14
5
4
14
5
4
33
12
10
17
6
5
8
3
2
25
175
35
30
150
30
26
150
30
26
150
30
26
60
12
10
6
T
amb
100
20
17
100
20
17
75
15
13
125
25
21
75
15
13
74HC
40 to 85
( C)
220
44
37
190
38
33
190
38
33
190
38
33
75
15
13
120
24
20
120
24
20
90
18
15
150
30
26
90
18
15
40 to 125
265
53
45
225
45
38
225
45
38
225
45
38
90
18
15
.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
74HC/HCT173
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
TEST CONDITIONS
V
(V)
Product specification
CC
Fig.6
Fig.7
Fig.8
Fig.8
Fig.6
Fig.6
Fig.7
Fig.7
Fig.9
Fig.9
WAVEFORMS