rs5c62 RICOH Co.,Ltd., rs5c62 Datasheet - Page 28

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rs5c62

Manufacturer Part Number
rs5c62
Description
Real-time Clock
Manufacturer
RICOH Co.,Ltd.
Datasheet

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24
7. Detection of Stop of Oscillation
bit is switched from “0” to “1” upon detection of the stop of oscillation. This principle can be used to check the valid-
ity of time data.
(The stop of oscillation can also be detected by using the software-controlled processes described in 11.1.2
Initialization Subject to Setting of XSTP Bit. “Initialization at Power-on”.)
Elements Involved in Timer
RP/RF/RS5C62
Timer clock selection register and TMFG bit
TMR bit
*
*
The stop of oscillation can be detected by monitoring the XSTP bit in the control register 2. Namely, the XSTP
It is recommended to update the settings of the timer clock selection register at regular time intervals to
improve the stability of timer operation.
Ensure error-free detection of the stop of oscillation by:
1) Preventing the VDD pin input from making instantaneous power disconnection.
2) Preventing the crystal oscillators causing condensation.
3) Preventing the crystal oscillators from causing noises on the PCB.
4) Preventing the individual pins from being impressed with voltage exceeding the maximum rating.
1) The XSTP bit is set to “1” at power-on from 0V. Note that the XSTP bit may be locked at instantaneous power disconnection.
2) Once the stop of oscillation has been detected, the XSTP bit is kept at “1” even after the restart of oscillation.
Power-on from 0V
XSTP
*
1
Setting the XSTP bit to “0”
(During oscillation)
Considerations in Using XSTP Bit
(See “2.9 Timer Clock Selection Register”)
(See “2.1 Control Register 1”)
Reference
Stop of oscillation
Restart of oscillation
*
2

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