mrf24j40 Microchip Technology Inc., mrf24j40 Datasheet - Page 32

• Manufacturer Part Number: mrf24j40
• Description: Ieee 802.15.4? 2.4 Ghz Rf Transceiver
• Manufacturer: Microchip Technology Inc.

7.2.1
The MRF24J40 handles the Clear Channel Assess-
ment (CCA) and Carrier Sense Multiple Access Colli-
sion Avoidance (CSMA-CA) algorithms in hardware.
The MRF24J40 also handles automatic retransmission
of packets that require an ACK. If the frame control field
REGISTER 7-1:
DS39776A-page 30
MRF24J40
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
This bit is cleared at the next triggering of TXN FIFO.
TRIGGER PACKET TRANSMISSION
Unimplemented: Read as ‘0’
PENDACK: Data Pending Status in ACK bit
Status of the data pending bit in ACK from previous transmission. This bit is reset by hardware on the
next transmission.
1 = Data pending bit was set
0 = Data pending bit was cleared
INDIRECT: Activate Indirect Transmission bit
1 = Indirect transmission enabled
0 = Indirect transmission disabled
ACKREQ: TX Packet in TXN FIFO needs ACK Response bit
1 = ACK requested
0 = No ACK requested
SECEN: Secure Current TX Packet bit
1 = Secure packet
0 = Send packet without securing it
TXRTS: Trigger TX MAC to Send the Packet in TX FIFO bit
1 = Send the packet in the TX FIFO, automatically cleared by hardware
U-0
—
TXNMTRIG: TRIGGER AND SETTING FOR NORMAL FRAME (CAP) REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
Advance Information
PENDACK
R-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
INDIRECT
(1)
R/W-0
of the packet requires an ACK, the ACKREQ bit
(TXNMTRIG<2>) needs to be set before transmission.
Once the TX FIFO is loaded with the data to transmit
the TXRTS bit (TXNMTRIG<0>) is used to transmit the
packet.
(1)
ACKREQ
(1)
R/W-0
(1)
© 2006 Microchip Technology Inc.
x = Bit is unknown
SECEN
R/W-0
(1)
TXRTS
W-0
bit 0