mrf24j40 Microchip Technology Inc., mrf24j40 Datasheet - Page 9

• Manufacturer Part Number: mrf24j40
• Description: Ieee 802.15.4? 2.4 Ghz Rf Transceiver
• Manufacturer: Microchip Technology Inc.

2.0
2.1
The MRF24J40 is designed to operate at 20 MHz with
a crystal connected to the OSC1 and OSC2 pins. A
typical oscillator circuit is shown in Figure 2-1.
FIGURE 2-1:
REGISTER 2-1:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4-0
Note 1:
R/W-0
C1
C2
r
EXTERNAL CONNECTIONS
Oscillator
A series resistor (R
strip cut crystals.
XTAL
R
S (1)
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
CLKOEN: 20 MHz Clock Output Enable bit
1 = Disable
0 = Enable
SCLKDIV4:SCLKDIV0: Divided SLPCLK Selection bits
Divided by 2
OSC2
OSC1
U-0
—
CRYSTAL OSCILLATOR
OPERATION
CLKCTRL: DIVIDED SLEEP CLOCK (50 kHz) SELECTION REGISTER
n
S
.
) may be required for AT
W = Writable bit
‘1’ = Bit is set
CLKOEN
MRF24J40
R/W-0
To Internal
Advance Information
Logic
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
2.2
The MRF24J40 PHY has an internal PLL that must lock
before the device is capable of transmitting or receiving
packets. After a full Power-on Reset, the device
requires 2 ms to lock. During this delay, all registers
and buffer memory may still be read and written to
through the SPI bus. However, software should not
attempt to transmit any packets (set the TXRTS
(TXNMTRIG<0>)), or access any MAC or PHY
registers during this period.
2.3
The clock out pin is provided to the system designer for
use as the host controller clock or as a clock source for
other devices in the system. The CLKOUT has an inter-
nal prescaler which can divide the output by 1, 2, 4 or 8.
The CLKOUT function is enabled via the CLKCTRL
register (Register 2-1) and the prescaler is selected via
the RFCTRL7 register (Register 2-2).
Oscillator Start-up
CLKOUT Pin
SCLKDIV<4:0>
R/W-0
x = Bit is unknown
MRF24J40
R/W-0
DS39776A-page 7
R/W-0
bit 0