74AUP1G80GM,132 NXP Semiconductors, 74AUP1G80GM,132 Datasheet
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74AUP1G80GM,132
Specifications of 74AUP1G80GM,132
74AUP1G80GM-H
935279051132
Related parts for 74AUP1G80GM,132
74AUP1G80GM,132 Summary of contents
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Low-power D-type flip-flop; positive-edge trigger Rev. 2 — 15 September 2010 1. General description The 74AUP1G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74AUP1G80GW −40 °C to +125 °C 74AUP1G80GM −40 °C to +125 °C 74AUP1G80GF −40 °C to +125 °C 74AUP1G80GN −40 °C to +125 °C 74AUP1G80GS 4. Marking Table 2. Marking ...
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... NXP Semiconductors CP D Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74AUP1G80 GND 001aac563 Fig 4. Pin configuration SOT353-1 6.2 Pin description Table 3. Pin description Symbol Pin TSSOP5 GND n. 74AUP1G80 Product data sheet Low-power D-type flip-flop; positive-edge trigger 74AUP1G80 GND 3 4 001aac522 Transparent top view Fig 5 ...
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... NXP Semiconductors 7. Functional description [1] Table 4. Function table Input CP ↑ ↑ HIGH voltage level LOW voltage level; ↑ = LOW-to-HIGH CP transition don’t care lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134) ...
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... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 25 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF Δ ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF Δ ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +125 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF Δ ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions propagation see pd delay maximum CP; see max frequency propagation see pd delay maximum CP; see max frequency 74AUP1G80 Product data sheet Low-power D-type flip-flop; positive-edge trigger Figure 9 25 ° ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions propagation see pd delay maximum CP; see max frequency propagation see pd delay maximum CP; see max frequency pF and set-up time D to CP; see su(H) HIGH V CC ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions t set-up time D to CP; see su(L) LOW hold time D to CP; see pulse width CP HIGH or LOW; W see Figure power MHz dissipation V = GND capacitance [1] All typical values are measured at nominal V ...
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... NXP Semiconductors 12. Waveforms D input CP input Q output Measurement points are given in Logic levels: V and Fig 7. The clock input (CP) to output (Q) propagation delays D input CP input Q output Measurement points are given in Logic levels: V and Fig 8. The clock input (CP) to output (Q) propagation delays, clock pulse width set-up and hold times and the maximum input clock frequency Table 9 ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 9. Test circuit for measuring switching times Table 10. ...
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... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION IEC SOT353-1 Fig 10 ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 12 ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date 74AUP1G80 v.2 20100915 • Modifications: Added type number 74AUP1G80GN (SOT1115/XSON6 package). ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AUP1G80 Product data sheet Low-power D-type flip-flop ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline ...