74AUP1G175GF,132 NXP Semiconductors, 74AUP1G175GF,132 Datasheet
![IC FLIP-FLOP D POS-EDGE 6-XSON](/photos/1/39/13915/6-xson_sot886_pkg_sml.jpg)
74AUP1G175GF,132
Specifications of 74AUP1G175GF,132
74AUP1G175GF-H
935281334132
Related parts for 74AUP1G175GF,132
74AUP1G175GF,132 Summary of contents
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Low-power D-type flip-flop with reset; positive-edge trigger Rev. 3 — 30 September 2010 1. General description The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74AUP1G175GW −40 °C to +125 °C 74AUP1G175GM −40 °C to +125 °C 74AUP1G175GF −40 °C to +125 °C 74AUP1G175GN −40 °C to +125 °C 74AUP1G175GS 4. Marking Table 2. Marking ...
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... NXP Semiconductors Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74AUP1G175 GND 001aaa467 Fig 4. Pin configuration SOT363 6.2 Pin description Table 3. Pin description Symbol Pin CP 1 GND 74AUP1G175 Product data sheet Low-power D-type flip-flop with reset; positive-edge trigger 74AUP1G175 GND 001aab657 Transparent top view Fig 5 ...
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... NXP Semiconductors 7. Functional description [1] Table 4. Function table Operating mode Input MR Reset (clear) L Load ‘1’ H Load ‘0’ HIGH voltage level HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition LOW voltage level LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; ...
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... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I input leakage current I I power-off leakage current OFF ΔI additional power-off OFF leakage current I supply current CC ΔI additional supply current CC C input capacitance I C output capacitance O = − ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I supply current CC ΔI additional supply current CC = −40 °C to +125 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay see see f maximum CP; see max frequency 74AUP1G175 Product data sheet Low-power D-type flip-flop with reset; positive-edge trigger Min [2] Figure ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay see see f maximum CP; see max frequency propagation delay see see 74AUP1G175 Product data sheet Low-power D-type flip-flop with reset; positive-edge trigger … ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions f maximum CP; see max frequency propagation delay see see f maximum CP; see max frequency 74AUP1G175 Product data sheet Low-power D-type flip-flop with reset; positive-edge trigger … ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and pulse width CP; HIGH or LOW; W see MR; LOW; see t recovery time MR; see rec t set-up time HIGH D to CP; see su(H) t set-up time LOW D to CP; see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t hold time D to CP; see h C power dissipation MHz capacitance V I [1] All typical values are measured at nominal V [ the same as t and PLH PHL [ used to determine the dynamic power dissipation (P PD × ...
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... NXP Semiconductors 12. Waveforms D input CP input Q output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical output voltage drop that occur with the output load Fig 7. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the set-up, the CP to ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 9. Test circuit for measuring switching times Table 10. ...
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... NXP Semiconductors 13. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 10. Package outline SOT363 (SC-88) 74AUP1G175 Product data sheet Low-power D-type flip-flop with reset; positive-edge trigger ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 12 ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date 74AUP1G175 v.3 20100930 • Modifications: Added type number 74AUP1G175GN (SOT1115/XSON6 package). ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AUP1G175 Product data sheet Low-power D-type flip-flop with reset ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Package outline ...