74ALVC74D,118 NXP Semiconductors, 74ALVC74D,118 Datasheet - Page 2

• Manufacturer Part Number: 74ALVC74D,118
• Description: IC DUAL D F-F POS-EDGE 14SOIC
• Manufacturer: NXP Semiconductors
• Series: 74ALVCr
• Type: D-Typer

Specifications of 74ALVC74D,118

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Function: Set(Preset) and Reset
• Output Type: Differential
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 275MHz
• Delay Time - Propagation: 3.7ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: ALVC
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 2.3 ns at 3.3 V
• High Level Output Current: - 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74ALVC74D-T; 74ALVC74D-T; 935269741118

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2003 May 26
t
t
f
C
C
PHL
PHL
max
SYMBOL
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
I
PD
Dual D-type flip-flop with set and reset;
positive-edge trigger
P
f
f
C
V
N = total load switching outputs;
i
o
/t
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
propagation delay nCP to nQ, nQ
propagation delay nSD, nRD to nQ, nQ
maximum clock frequency
input capacitance
power dissipation capacitance per buffer
2
V
CC
= 25 C.
f
o
2
) = sum of the outputs.
I
f
= GND to V
i
N + (C
PARAMETER
L
CC
.
V
CC
2
f
o
) where:
V
V
V
V
V
V
V
V
V
2
CC
CC
CC
CC
CC
CC
CC
CC
CC
DESCRIPTION
The 74ALVC74 is a dual positive-edge triggered, D-type
flip-flop with individual data (D), clock (CP), set (SD) and
reset (RD) inputs and complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
= 1.8 V; C
= 2.5 V; C
= 2.7 V; C
= 3.3 V; C
= 1.8 V; C
= 2.5 V; C
= 2.7 V; C
= 3.3 V; C
= 3.3 V; notes 1 and 2
D
in W).
CONDITIONS
L
L
L
L
L
L
L
L
= 30 pF; R
= 30 pF; R
= 50 pF; R
= 50 pF; R
= 30 pF; R
= 30 pF; R
= 50 pF; R
= 50 pF; R
L
L
L
L
L
L
L
L
= 1 k
= 500
= 500
= 500
= 1 k
= 500
= 500
= 500
Product specification
3.7
2.6
2.8
2.7
3.5
2.5
3.1
2.3
425
3.5
35
TYPICAL
74ALVC74
ns
ns
ns
ns
ns
ns
ns
ns
MHz
pF
pF
UNIT