50s116t Ceramate Technical Co., Ltd., 50s116t Datasheet - Page 12

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50s116t

Manufacturer Part Number
50s116t
Description
Sdram 512k X 2 Banks X 16 Bits Sdram
Manufacturer
Ceramate Technical Co., Ltd.
Datasheet
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Fax:886-3-3521052
8. TABLE OF OPERATING MODES
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 3 shows the truth table for the operation commands.
Table 3 Truth Table (Note 1, 2)
Notes:
(1) V = Valid, X = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input level when commands are provided.
(3) These are state of bank designated by BA signals.
(4) Device state is full page burst operation.
(5) Power-down Mode can not be entered in the burst cycle.
Bank Active
Bank Precharge
Precharge All
Write
Write with Auto
Precharge
Read
Read with Auto
Precharge
Mode Register Set
No Operation
Burst Stop
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Clock Suspend Mode
Entry
Power-down Mode Entry
Clock Suspend Mode
Exit
Power-down Mode Exit
Data Write/Output
Enable
Data Write/Output
Disable
When this command asserts in the burst cycle, device state is clock suspend mode.
COMMAND
Active (3)
Active (3)
Active (3)
Active (3)
Active (4)
Active (5)
DEVICE
STATE
(Power-
Active
Active
Active
Active
down)
(S.R)
Any
Any
Any
Any
Any
Idle
Idle
Idle
Idle
Idle
Idle
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
CKEn
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
X
X
L
L
L
L
Page 12 of 42
DQM
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
BA
V
V
X
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A10
V
H
H
H
V
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A9-0
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
V
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CS
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
L
X
X
50S116T
RAS CAS
H
H
H
H
H
H
H
H
H
Rev 1.0 Aug.20,2002
L
L
L
L
X
L
L
X
X
X
X
X
X
X
H
H
H
H
H
X
X
H
X
X
H
X
X
H
X
X
L
L
L
L
L
L
L
SDRAM
WE
H
H
H
H
H
H
L
L
L
L
L
L
X
X
H
X
X
H
X
X
H
X
X

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