50s116t Ceramate Technical Co., Ltd., 50s116t Datasheet - Page 3

• Manufacturer Part Number: 50s116t
• Description: Sdram 512k X 2 Banks X 16 Bits Sdram
• Manufacturer: Ceramate Technical Co., Ltd.

* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
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Fax:[phone]
1. GENERAL DESCRIPTION
50S116T is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words
bandwidth of up to 400M bytes per second (-5). For different applications the 50S116T is
sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200MHz/CL3.
The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For
handheld device application.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. 50S116T is ideal for main memory in
high performance applications.
2. FEATURES
3. AVAILABLE PART NUMBER
50S116T-5
50S116T-6
50S116T-7
3.3V 0.3V power supply
Up to 200 MHz clock frequency
524,288 words x 2 banks x 16 bits organization
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst read, Single Write Mode
Byte data controlled by UDQM and LDQM
Auto precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in 50-pin, 400 mil TSOP II
PART NUMBER
2 banks
16 bits. Using pipelined architecture 50S116T delivers a data
SPEED (CL = 3 )
200 MHz
166 MHz
143 MHz
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Http: www.ceramate.com.tw
1 mA
1 mA
1 mA
50S116T
Rev 1.0 Aug.20,2002
SDRAM