50s116t Ceramate Technical Co., Ltd., 50s116t Datasheet - Page 9

• Manufacturer Part Number: 50s116t
• Description: Sdram 512k X 2 Banks X 16 Bits Sdram
• Manufacturer: Ceramate Technical Co., Ltd.

* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:[phone]
Fax:[phone]
edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the
during a full page burst write operation, then any residual data from the burst write cycle will be
ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address, which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 1.
Table 1 Address Sequence of Sequential Mode
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in
the sequence shown in Table 2.
Table 2 Address Sequence of Interleave Mode
CAS
Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
DATA
ACCESS ADDRESS
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
A8 A7 A6 A5 A4 A3
A8 A7 A6 A5 A4 A3
A8 A7 A6 A5 A4 A3
A8 A7 A6 A5 A4 A3 A2
A8 A7 A6 A5 A4 A3
A8 A7 A6 A5 A4 A3 A2
n
A8 A7 A6 A5 A4 A3 A2 A1
A8 A7 A6 A5 A4 A3 A2 A1 A0
ACCESS ADDRESS
BL = 8 (disturb addresses are A0, A1 and A2)
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BL = 4 (disturb addresses are A0 and A1)
A2
A2
A2
A2
No address carry from A0 to A1
No address carry from A1 to A2
No address carry from A2 to A3
BL = 2 (disturb address is A0)
A1
A1 A0
A1
A1
A1 A0
A1 A0
A0
A0
BURST LENGTH
A0
A0
BUST LENGTH
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BL = 2
BL = 4
BL = 8
50S116T
Rev 1.0 Aug.20,2002
SDRAM