IDT74ALVCH16823PAG8 IDT, Integrated Device Technology Inc, IDT74ALVCH16823PAG8 Datasheet

IDT74ALVCH16823PAG8

Manufacturer Part Number

IDT74ALVCH16823PAG8

Description

IC FLIP FLOP 18BIT 3ST 56-TSSOP

Manufacturer

IDT, Integrated Device Technology Inc

Series

74ALVCHr

Type

D-Typer

Datasheet

1.IDT74ALVCH16823PAG8.pdf (7 pages)

Specifications of IDT74ALVCH16823PAG8

Function

Master Reset

Output Type

Tri-State Non Inverted

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

150MHz

Delay Time - Propagation

1ns

Trigger Type

Positive Edge

Current - Output High, Low

24mA, 24mA

Voltage - Supply

2.7 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74ALVCH16823PAG8

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FEATURES:

• 0.5 MICRON CMOS Technology

• Typical t

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

• V

• CMOS power levels (0.4μ μ μ μ μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FUNCTIONAL BLOCK DIAGRAM

CLKEN

IDT74ALVCH16823

3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

machine model (C = 200pF, R = 0)

CLR

CLK

= 3.3V ± 0.3V, Normal Range

= 2.7V to 3.6V, Extended Range

= 2.5V ± 0.2V

INDUSTRIAL TEMPERATURE RANGE

SK(o)

(Output Skew) < 250ps

TO 8 OTHER CHANNELS

3.3V CMOS 18-BIT

BUS-INTERFACE FLIP-

FLOP WITH 3-STATE OUT-

PUTS AND BUS-HOLD

CLKEN

DESCRIPTION:

technology. The ALVCH16823 features 3-state outputs designed specifically

for driving highly capacitive or relatively low-impedance loads. The device is

particularly suitable for implementing wider buffer registers, I/O ports, bidirec-

tional bus drivers with parity, and working registers.

With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the

low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer,

thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs

to go low independently of the clock.

in either a normal logic state (high or low logic levels) or a high-impedance state.

In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the

capability to drive bus lines without need for interface or pullup components. The

OE input does not affect the internal operation of the flip-flops. Old data can be

retained or new data can be entered while the outputs are in the high-impedance

state.

driver is capable of driving a moderate to heavy load while maintaining speed

performance.

whenever the input goes to a high impedance. This prevents floating inputs and

eliminates the need for pull-up/down resistor.

CLR

This 18-bit bus-interface flip-flop is built using advanced dual metal CMOS

The ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop.

A buffered output-enable (OE) input can be used to place the nine outputs

The ALVCH16823 has been designed with a ±24mA output driver. This

The ALVCH16823 has “bus-hold” which retains the inputs’ last state

CLK

INDUSTRIAL TEMPERATURE RANGE

TO 8 OTHER CHANNELS

IDT74ALVCH16823

OCTOBER 2008

DSC-4237/4

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IDT74ALVCH16823PAG8 Summary of contents

Page 1

IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS FEATURES: • 0.5 MICRON CMOS Technology • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R ...

Page 2

IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS PIN CONFIGURATION 1 CLR GND ...

Page 3

IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW ...

Page 4

IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS OUTPUT DRIVE CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL NOTE and V must be within the min. or max. range shown in the ...

Page 5

IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SWITCHING CHARACTERISTICS Symbol Parameter f MAX t Propagation Delay PLH t xCLK to xQx PHL t Propagation Delay PLH xCLR to xQx t PHL t Output Enable Time PZH xOE to ...

Page 6

IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 ...

Page 7

IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS ORDERING INFORMATION ALVC X XXX XX Temp. Range Bus-Hold Family CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XX XXX Device Type Package PA PAG 823 16 H ...

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