IDT74ALVCH16721PAG IDT, Integrated Device Technology Inc, IDT74ALVCH16721PAG Datasheet

IDT74ALVCH16721PAG

Manufacturer Part Number

IDT74ALVCH16721PAG

Description

IC FLIP FLOP 20BIT 3ST 56-TSSOP

Manufacturer

IDT, Integrated Device Technology Inc

Series

74ALVCHr

Type

D-Typer

Datasheet

1.IDT74ALVCH16721PAG8.pdf (6 pages)

Specifications of IDT74ALVCH16721PAG

Function

Set(Preset) and Reset

Output Type

Tri-State Non Inverted

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

150MHz

Delay Time - Propagation

1ns

Trigger Type

Positive Edge

Current - Output High, Low

24mA, 24mA

Voltage - Supply

2.7 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74ALVCH16721PAG

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FEATURES:

• 0.5 MICRON CMOS Technology

• Typical t

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

• V

• CMOS power levels (0.4μ μ μ μ μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Low switching noise

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

FUNCTIONAL BLOCK DIAGRAM

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16721

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

machine model (C = 200pF, R = 0)

= 3.3V ± 0.3V, Normal Range

= 2.7V to 3.6V, Extended Range

= 2.5V ± 0.2V

SK(o)

(Output Skew) < 250ps

CLKEN

CLK

3.3V CMOS 20-BIT

FLIP-FLOP WITH 3-STATE

OUTPUTS AND BUS-HOLD

TO 19 OTHER CHANNELS

DESCRIPTION:

20 flip-flops of the ALVCH16721 are edge-triggered D-type flip-flops with

qualified clock storage. On the positive transition of the clock (CLK) input, the

device provides true data at the Q outputs if the clock-enable (CLKEN) input

is low. If CLKEN is high, no data is stored.

logic state (high or low) or a high-impedance state. In the high-impedance state,

the outputs neither load nor drive the bus lines significantly. The high-

impedance state and increased drive provide the capability to drive bus lines

without need for interface or pullup components. OE does not affect the internal

operation of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

driver is capable of driving a moderate to heavy load while maintaining speed

performance.

whenever the input goes to a high impedance. This prevents floating inputs

and eliminates the need for pull-up/down resistor.

This 20-bit flip-flop is built using advanced dual metal CMOS technology. The

A buffered output-enable (OE) input places the 20 outputs in either a normal

The ALVCH16721 has been designed with a ±24mA output driver. This

The ALVCH16721 has “bus-hold” which retains the inputs’ last state

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16721

JULY 2009

DSC-4747/5

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IDT74ALVCH16721PAG Summary of contents

Page 1

IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS FEATURES: • 0.5 MICRON CMOS Technology • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF ...

Page 2

IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS PIN CONFIGURATION GND GND ...

Page 3

IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW Voltage ...

Page 4

IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS OUTPUT DRIVE CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL NOTE and V must be within the min. or max. range shown in the DC ...

Page 5

IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 300 ...

Page 6

IDT74ALVCH16721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS ORDERING INFORMATION ALVC XX X XXX Temp. Range Bus-Hold Family CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XXX XX Device Type Package PAG Thin Shrink Small Outline Package ...

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