sc28l198 NXP Semiconductors, sc28l198 Datasheet - Page 23

• Manufacturer Part Number: sc28l198
• Description: Octal Uart For 3.3v And 5v Supply Voltage
• Manufacturer: NXP Semiconductors

Philips Semiconductors
10110
10111
11000
Table 9. Command Register Code
Commands x’12, x13, x’14, x’15, x’1f (marked with*) are global and exist only in channel A’s register space.
Table 10. SR – Channel Status Register
SR[7] – Received Break
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received; further entries to the
FIFO are inhibited until the RxD line returns to the marking state for
at least one half bit time (two successive edges of the internal or
external 1x clock). When this bit is set, the change in break bit in
the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break
condition, as defined above, is detected. The break detect circuitry
2006 Aug 10
Channel Command
Code
CR[7:3]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Bit 7
Received
Break
0 – No
1 – Yes
Octal UART for 3.3 V and 5 V supply voltage
mechanism to initialize all the Xoff Character registers to a
default value with one write. Execution of this command
is immediate and does not effect the timing of subsequent
host I/O operations.
Xoff resume command (CRXoffre; not active in
“Auto-Transmit Mode”). A command to cancel a previous
Host Xoff command. Upon receipt, the channel’s
transmitter will transfer a character, if any, from the
TxFIFO and begin transmission.
Host Xoff command (CRXoff). This command allows tight
host CPU control of the flow control of the channel
transmitter. When interrupted for receipt of an Xoff
character by the receiver, the host may stop transmission
of further characters by the channel transmitter by issuing
the Host Xoff command. Any character that has been
transferred to the TxD shift register will complete its
transmission, including the stop bit.
Cancel Host transmit flow control command. Issuing this
command will cancel a previous transmit command if the
Bit 6
Framing Error
0 – No
1 – Yes
Channel
Command
Description
NOP
Reserved
Reset Receiver
Reset Transmitter
Reset Error Status
Reset Break Change Interrupt
Begin Transmit Break
End Transmit Break
Assert RTSN (I/O2 or I/O1)
Negate RTSN (I/O2 or I/O1)
Set time–out mode on
Reserved
Set time–out mode off
Block Error Status configure
Reserved
Reserved
Bit 5
Parity
Error
0 – No
1 – Yes
Bit 4
Overrun Error
0 – No
1 – Yes
Channel Command
Code
CR[7:3]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
23
Bit 3
TxEMT
0 – No
1 – Yes
11001–11011
11011 Reset Address Recognition Status. This command clears the
11100–11101
11110
11111
is capable of detecting breaks that originate in the middle of a
received character. However, if a break begins in the middle of a
character, it must last until the end of the next character in order for
it to be detected.
SR[6] – Framing Error (FE)
This bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
flow control character is not yet loaded into the TxD Shift
Register. If there is no character waiting for transmission
or if its transmission has already begun, then this
command has no effect.
Reserved
interrupt status that was set when an address character
was recognized by a disabled receiver operating in the
special mode.
Reserved
Resets all UART channel registers. This command
provides a means to zero all the UART channels that are
not reset to x’00 by a reset command or a hardware reset.
Reserved for channels b-h, for channel a: executes a chip
wide reset. Executing this command in channel a is
equivalent to a hardware reset with the RESETN pin.
Executing in channel b-h, has no effect.
Bit 2
TxRDY
0 – No
1 – Yes
Channel
Command
Description
Transmit Xon
Transmit Xoff
Gang Write Xon Character Registers *
Gang Write Xoff Character Registers *
Gang Load Xon Character Registers DC1 *
Gang Load Xoff Character Registers DC3 *
Xoff Resume Command
Host Xoff Command
Cancel Transmit X Char command
Reserved
Reserved
Reset Address Recognition Status
Reserved
Reserved
Reset All UART channel registers
Reset Device *
Bit 1
RxFULL
0 – No
1 – Yes
SC28L198
Product data sheet
Bit 0
RxRDY
0 – No
1 – Yes