st10f273m STMicroelectronics, st10f273m Datasheet - Page 150

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st10f273m

Manufacturer Part Number
st10f273m
Description
16-bit Mcu With 512 Kbyte Flash Memory And 36 Kbyte Ram
Manufacturer
STMicroelectronics
Datasheet

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Electrical characteristics
24.8.7
24.8.8
150/182
an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct
clock input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct
Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply
current.
Phase locked loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see
frequency by the factor F which is selected via the combination of pins P0.15-13 (f
f
the input clock. This synchronization is done smoothly, so the CPU clock frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of f
locked to f
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f
keep it locked on f
one TCL period.
This is especially important for bus cycles using wait states and for example, such as for the
operation of timers or serial interfaces. For all slower operations and longer periods (for
example, such as pulse train generation or measurement, or lower baudrates) the deviation
caused by the PLL jitter is negligible. Refer to the next
details.
Voltage controlled oscillator
The ST10F273M implements a PLL which combines different levels of frequency dividers
with a Voltage Controlled Oscillator (VCO) working as frequency multiplier.
page 151
XTAL
x F). With every F’th transition of f
gives a detailed summary of the internal settings and VCO frequency.
XTAL
. The slight variation causes a jitter of f
XTAL
. The relative deviation of TCL is the maximum when it is referred to
XTAL
the PLL circuit synchronizes the CPU clock to
Table
CPU
Section 24.8.9: PLL jitter
62). The PLL multiplies the input
which also effects the duration of
CPU
is constantly adjusted so it is
Table 63 on
ST10F273M
for more
CPU
CPU
to
=

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