st10f273m STMicroelectronics, st10f273m Datasheet - Page 157

• Manufacturer Part Number: st10f273m
• Description: 16-bit Mcu With 512 Kbyte Flash Memory And 36 Kbyte Ram
• Manufacturer: STMicroelectronics

ST10F273M
24.8.14
24.8.15
Note:
24.8.16
Table 71.
Symbol
t
t
t
t
t
t
t
t
t
t
5
6
7
8
9
10
11
12
13
14
CC ALE high time
CC Address setup to ALE
CC Address hold after ALE
CC
CC
CC
CC
CC
CC
SR
ALE falling edge to RD, WR
(with RW-delay)
ALE falling edge to RD, WR (no
RW-delay)
Address float after RD, WR
(with RW-delay)
Address float after RD, WR (no
RW-delay)1
RD, WR low time
(with RW-delay)
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes how these variables are to be computed.
Table 70.
External memory bus timing
The following sections present the External Memory Bus timings. The given values are
computed for a maximum CPU clock of 40 MHz.
All external memory bus timings and SSC timings reported in the following tables are based
on design characterization and not fully tested in production.
Multiplexed bus
V
ALE cycle time = 6 TCL + 2t
Multiplexed bus timings
ALE Extension
Memory Cycle Time wait states
Memory Tri-stateTime
DD
= 5V ± 10%, V
Parameter
Description
Memory cycle variables
SS
= 0V, T
15.5 + t
-8.5 + t
1.5 + t
28 + t
A
4 + t
4 + t
4 + t
Min
A
+ t
–
–
–
= -40 to +125°C, CL = 50pF,
f
TCL = 12.5ns
CPU
A
A
A
C
C
A
A
C
+ t
= 40 MHz
F
Symbol
(75ns at 40 MHz CPU clock without wait states)
6 + t
t
t
Max
18.5
t
A
C
F
–
–
–
–
–
6
–
–
C
TCL x [ALECTL]
2TCL x (15 - [MCTC])
2TCL x (1 - [MTTC])
2TCL - 9.5 + t
3TCL - 9.5 + t
TCL - 8.5 + t
TCL - 8.5 + t
TCL - 8.5 + t
TCL - 11 + t
-8.5 + t
Min
1/2 TCL = 1 to 40 MHz
–
–
–
Variable CPU clock
A
A
A
A
A
C
C
Electrical characteristics
Values
2TCL - 19 + t
TCL + 6
Max
–
–
–
–
–
6
–
–
C
157/182
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns