ds3171n Maxim Integrated Products, Inc., ds3171n Datasheet - Page 164
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ds3171n
Manufacturer Part Number
ds3171n
Description
Ds3171, Ds3172, Ds3173, Ds3174 Single/dual/triple/quad Ds3/e3 Single-chip Transceivers
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3171N.pdf
(234 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: The FIFO data and status are updated when the Receive FIFO Data (RFD[7:0]) is read (upper byte read).
When this register is read eight bits at a time, a read of the lower byte will reflect the status of the next read of the
upper byte, and reading the upper byte when RFDV=0 may result in a loss of data.
Bits 15 to 8: Receive FIFO Data (RFD[7:0]) – These eight bits are the packet data stored in the Receive FIFO.
RFD[7] is the MSB, and RFD[0] is the LSB. If bit reordering is disabled, RFD[0] is the first bit received, and RFD[7]
is the last bit received. If bit reordering is enabled, RFD[7] is the first bit received, and RFD[0] is the last bit
received.
Bits 3 to 1: Receive Packet Status (RPS[2:0]) – These three bits indicate the status of the received packet and
packet data.
Bit 0: Receive FIFO Data Valid (RFDV) – When 0, the Receive FIFO data (RFD[7:0]) is invalid (the Receive FIFO
is empty). When 1, the Receive FIFO data (RFD[7:0]) is valid.
000 = packet middle
001 = packet start.
010 = reserved
011 = reserved
100 = packet end: good packet
101 = packet end: FCS errored packet.
110 = packet end: invalid packet (a non-integer number of bytes).
111 = packet end: aborted packet.
RFD7
15
X
--
7
0
RFD6
14
X
--
6
0
HDLC.RFDR
HDLC Receive FIFO Data Register
(0,2,4,6)BCh
RFD5
13
X
--
5
0
RFD4
12
X
--
0
4
164
RFD3
RPS2
11
X
X
3
RFD2
RPS1
10
X
X
2
RFD1
RPS0
X
X
9
1
RFDV
RFD0
X
8
0
0
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