SSTUA32S865 NXP Semiconductors, SSTUA32S865 Datasheet - Page 8

• Manufacturer Part Number: SSTUA32S865
• Description: Sstua32s865 1.8 V 28-bit 1 2 Registered Buffer With Parity For Ddr2-667 Rdimm Applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Functional description
Table 3.
[1]
Table 4.
[1]
SSTUA32S865_2
Product data sheet
RESET
RESET
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated
correctly.
L
H
H
H
H
H
H
H
H
H
H
L
0
is the previous state of the associated output.
Function table (each flip-flop)
Parity and standby function table
floating
DCS0
X or floating
X or
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
DCS0
7.1 Function table
H
H
H
H
H
X
L
L
L
L
floating
DCS1
X or
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
X or floating
DCS1
H
H
H
H
H
X
L
L
L
L
CSGATEEN
X or floating
Inputs
H
H
H
X
X
X
X
X
X
X
X
X
L
L
L
X or floating
L or H
CK
Inputs
Rev. 02 — 16 March 2007
floating
L or H
L or H
L or H
L or H
L or H
X or
CK
X or floating
L or H
floating
CK
L or H
L or H
L or H
L or H
L or H
X or
CK
1.8 V DDR2-667 registered buffer with parity
Dn, DODTn,
X or floating
DCKEn
(D0 to D21)
X or floating
of inputs = H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
even
even
even
even
odd
odd
odd
odd
X
X
Qn
Q
Q
Q
Q
Q
Q
Q
H
H
H
H
L
L
L
L
L
SSTUA32S865
0
0
0
0
0
0
0
X or floating
PARIN
QCS0
Q
Q
Q
Q
Q
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
X
X
0
0
0
0
0
Outputs
[1]
© NXP B.V. 2007. All rights reserved.
QCS1
Q
Q
Q
Q
Q
H
H
H
H
H
H
L
L
L
L
L
0
0
0
0
0
[1]
PTYERR
PTYERR
PTYERR
Output
QODTn,
QCKEn
H
H
H
H
H
L
L
L
L
Q
Q
Q
Q
Q
H
H
H
H
H
L
L
L
L
L
L
[2][3]
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0
0
0
0
0
0
0