cs4244-enzr Cirrus Logic, Inc., cs4244-enzr Datasheet
cs4244-enzr
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cs4244-enzr Summary of contents
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... Digital volume control, noise gating, and muting is provided for each DAC path. A se- lectable high-pass filter is provided for the 4 ADC inputs. The CS4244 supports master and slave modes and TDM, left-justified, and I²S modes. This product is available in a 40-pin QFN package in Automotive (-40 ° ...
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... Interrupt Control (Address 1Eh) ................................................................................................... 56 6.16 Interrupt Mask 1 (Address 1Fh) ................................................................................................... 57 6.17 Interrupt Mask 2 (Address 20h) ................................................................................................... 58 6.18 Interrupt Notification 1 (Address 21h) (Read Only) ...................................................................... 58 6.19 Interrupt Notification 2 (Address 22h) (Read Only) ...................................................................... 59 7. ADC FILTER PLOTS ............................................................................................................................ 60 8. DAC FILTER PLOTS ............................................................................................................................ 61 9. PACKAGE DIMENSIONS ................................................................................................................... 63 10. ORDERING INFORMATION .............................................................................................................. 64 11. REVISION HISTORY .......................................................................................................................... 65 DS900PP2 ................................................................................................... 7 ....................................................................... 48 CS4244 2 ...
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... LIST OF FIGURES Figure 1. CS4244 Pinout ............................................................................................................................. 5 Figure 2. Typical Connection Diagram ........................................................................................................ 7 Figure 3. Test Circuit for ADC Performance Testing ................................................................................. 13 Figure 4. PSRR Test Configuration ........................................................................................................... 13 Figure 5. Equivalent Output Test Load ..................................................................................................... 16 Figure 6. TDM Serial Audio Interface Timing ............................................................................................ 20 Figure 7. PCM Serial Audio Interface Timing ............................................................................................ 20 Figure 8. I²C Control Port Timing .............................................................................................................. 21 Figure 9 ...
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... Table 3. Master Mode Left Justified and I²S Clock Ratios ........................................................................ 27 Table 4. Slave Mode Left Justified and I²S Clock Ratios .......................................................................... 27 Table 5. Slave Mode TDM Clock Ratios ................................................................................................... 27 Table 6. Soft Ramp Rates ......................................................................................................................... 41 Table 7. Noise Gate Bit Depth Settings .................................................................................................... 42 Table 8. Error Reporting and Interrupt Behavior Details ........................................................................... 43 DS900PP2 CS4244 4 ...
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... The full scale analog input level is specified in the Analog Input Characteristics tables on pages 18 and 12. FILT+ 19 Positive Voltage Reference (Output) - Positive reference voltage for the internal ADCs. DS900PP2 Top-Down 5 (Though Package) 6 View Figure 1. CS4244 Pinout Pin Description CS4244 AOUT2+ 30 AOUT2- 29 AOUT3+ 28 AOUT3- 27 AOUT4+ 26 AOUT4- 25 VBIAS 24 VREF 23 VQ ...
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... Input/Output 5.0 V CMOS Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis Output 5.0 V CMOS Weak Pull-down (~500k Input - Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis Input - (Note 2) (Note 2) Figure 2. CS4244 Analog Output Characteristics Analog Output Characteristics for more details concerning this mode of Receiver - 5.0 V CMOS, with Hysteresis 5.0 V CMOS 5.0 V CMOS 6 ...
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... Down Based upon Desired *** Address CS4244 1uF Figure 2. Typical Connection Diagram CS4244 Analog Output Filter * 31 AOUT2+ 30 Analog Output Filter * AOUT2- 29 AOUT3+ 28 Analog Output Filter * AOUT3- 27 AOUT4+ 26 Analog Output Filter * AOUT4- 25 VBIAS 24 10uF VREF 23 0.1uF VQ ...
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... Automotive - Commercial -20 T -40 J Symbol Min VA -0.3 VL -0.3 (Note 4) I VDREG (Note (Note 0.3 INA (Note 6) V -0.3 IND T - -65 stg CS4244 Typ Max Units 3.3 3.465 5.25 V C - +105 C - +85 C - +150 Max Units 5.5 V 5.5 V ± 0 ...
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... Nominal Voltage Output Impedance DC Current Source/Sink VQ Nominal Voltage Output Impedance DC Current Source/Sink Notes external loads should be connected to the VDREG pin. Any connection of a load to this point may result in errant operation or performance degradation in the device. DS900PP2 CS4244 Min Typ Max Units - 2 - ...
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... PLL is activated by setting the MCLK RATE bit to either 000 (operating in 256x mode) or 001 (operating in 384kHz). 11. Internal to the CS4244, the analog to digital converters are grouped together in stereo pairs. ADC1 and ADC2 are grouped together as are ADC3 and ADC4. The ADC group current draw is the current that is drawn whenever one of these groups become active ...
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... CS4244 Section 2. on page 7. Input sine bits = 0. See (Note 13). VA, VREF = 5.0 V Typ Max Unit 105 - dB 102 - dB - -88 - - ±100 - ppm/°C - 0.0001 - % Full Scale - 0. Full Scale ...
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... Enable High-pass Filter register bit disabled and Enable High-pass Filter CS4244 Section 2. on page 7. Input sine Power Down ADCx bits = 0. See (Note VA, VREF = 5.0 V Min Typ Max Unit 97 105 - 94 102 - - -88 ...
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... VA 470 pF 634 +Vcc Operational Amplifier - + -Vcc Test Equipment Figure 4. PSRR Test Configuration CS4244 90.9 CS4244 AINx + 2700 pF CS4244 AINx - 90.9 DUT PWR GND Analog Digital Out Out - + - + - + Analyzer 13 ...
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... SDOUTx. 18. The amount of time from input of half-full-scale step function until the filter output settles to 0.1% of full scale. DS900PP2 = -40 to +105 C; Measurement Bandwidth is A Section 7. on page (Note 16) to -0.1 dB corner CS4244 Section 2. on page 7. Input sine 60. Min Typ Max Unit ...
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... CS4244 Section 2. on page 7. VA_SEL = 0 for Power VA, VREF= 5.0 V (Differential/Single-ended) Min Typ Max Unit 103/99 109/105 - 100/96 106/102 - -90/-88 -84/-82 1.48•VA/ 1.56•VA/ 1.64•VA/ 0.74•VA 0.78•VA 0.82•VA - 100 - - 0.1 0.25 - ±100 - ppm/°C ...
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... Figure 5 below. 22 µF AOUTx R L GND Figure 5. Equivalent Output Test Load Section 4.2.3. CS4244 Section 2. on page 7. VA_SEL = 0 for VA, VREF= 5.0 V (Differential/Single-ended) Min Typ Max Unit 101/97 109/105 - 98/94 106/102 - -90/-88 -82/-80 1.48•VA/ 1.56•VA/ 1.64•VA/ 0.74•VA 0.78•VA 0.82•VA - 100 - - 0 ...
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... SDINx pins to the time it appears on the AOUTx pins. DS900PP2 VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC. The filter charac- ) and can be referenced to the desired sample rate by multi -0.05 dB corner corner (Note 24) to -0.1 dB corner corner (Note 24 CS4244 Min Typ Max 0 - 0.4780 0 - 0.4996 -0.01 - +0.12 0.5465 - - ...
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... Low-Level Output Voltage Input Leakage Current Input Capacitance DS900PP2 Symbol ) (% of VL) RST VL) RST VL) V RST VL VL CS4244 Min Typ Max Units 75 70 30 0 20% V ± ...
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... MCLK CS4244 RST . S Master Clock Rate CS4244 Min Max Units - ms 1 7.68 25.6 MHz kHz 60 100 kHz - ...
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... Figure 6. TDM Serial Audio Interface Timing FS/LRCK (input/output) SCLK (input/output) SDINx (input) SDOUTx (output) Figure 7. PCM Serial Audio Interface Timing DS900PP2 t LPW dh1 MSB t t dh2 dh2 MSB t lcks dh1 MSB MSB-1 t dh2 MSB MSB-1 CS4244 MSB-1 MSB-1 20 ...
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... Setup Time for Stop Condition SDA Bus Load Capacitance SDA Pull-Up Resistance Notes: 31. All specifications are valid for the signals at the pins of the CS4244 with the specified load capacitance. 32 (3000/MCLK). See 33. Data must be held for sufficient time to bridge the transition time, t RST ...
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... Power-up The CS4244 enters a reset state upon the initial application of VA and VL. When these power supplies are initially applied to the device, the audio outputs, AOUTxx, are clamped to VQ which is initially low. Additionally, the interpolation and decimation filters, delta-sigma modulators and control port registers are all reset and the internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and low-pass filters are powered down ...
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... SDOUTx unmute behavior delay dependent on DAC mute / DACx Fully unmute behavior Operational System Operational ) on the output pins will be in parallel when the switch- x CS4244 Figure 9. If Clear RST 50 ms Set VQ_RAMP bit Set Mute ADCx bits Set Mute DACx bits 15 23 ...
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... External VQ ~140kΩ capacitor S3± AOUT3- AOUT4+ S4± AOUT4- Figure 10. DAC DC Loading acts as an I²C slave device. CS4244 CS4244 Switching Specifi- is released from reset. CS4244 24 ...
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... AD2 AD1 AD0 1 INCR ACK START Figure 12. Timing, I²C Read CS4244 and Figure 12. A Start condition is de- CS4244 , the chip address CS4244 from the microcontroller after each trans DATA +1 DATA + ...
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... System Clocking The CS4244 will operate at sampling frequencies from 30 kHz to 100 kHz. This range is divided into two speed modes as shown in The serial port clocking must be changed while all PDNx bits are set. If the clocking is changed otherwise, the device will enter a mute state, see 4 ...
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... Refer to S SSM 256x, 384x, 512x 32x, 48x, 64x, 128x SSM 256x, 384x, 512x 512x 256x 512x Table 5. Slave Mode TDM Clock Ratios CS4244 00 FS/LRCK 01 00 SCLK 01 below. DSM 128x, 192x, 256x 64x Table 4 ...
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... The serial port interface format is selected by the able in Slave Mode only. 4.5.1 TDM Mode The serial port of the CS4244 supports the TDM interface format with varying bit depths from shown in Figure 15. Data is clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge ...
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... DS900PP2 CS4244 29 ...
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... Left Justified and I²S Modes The serial port of the CS4244 supports the Left Justified and I²S interface formats with valid bit depths of 16, 18, 20 bits for the SDOUTx pins and 24 bits for the SDINx pins. All data is valid on the rising edge of SCLK ...
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... ADC Signal Routing In TDM mode, the CS4244 is designed to load the first four slots of the TDM stream on the SDOUT1 pin with the internal ADC data. Additionally, in order to minimize the number of SDOUT lines that must be run to the system controller in a multiple IC application, the SDOUT data for devices can be loaded ...
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... DAC1-4 path is located within the incoming TDM streams. Details for this register and the bit settings can be found in In Left Justified or I²S mode, the CS4244 routes the data on the SDIN1 pin to DAC1 and DAC2 and the data on the SDIN2 pin to DAC3 and DAC4. ...
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... DS900PP2 CS4244 33 ...
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... DS900PP2 CS4244 34 ...
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... SDIN2 SDIN1 Master Clock In Clock / LRCK Figure 23. ADC Path "SP Data Sel." register to be set to a ‘1’. 6.144 MHz), where n = 0,1,2,... Refer to CS4244 AOUT1 (±) AOUT2 (±) DAC & AOUT3 (±) Multi-bit Analog AOUT4 (±) Modulators Filters ...
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... DC offset error when the HPF is enabled or disabled. 634 470 pF C0G - 91 + 634 470 pF C0G - + 0.01 F 22 F CS4244 ADC1-4 * Place close to AINx pins AINx+ 634 2700 pF * C0G 91 AINx- 7. The Analog Input Characteristics ta- ADC1-4 * Place close to AINx pins AINx+ 634 ...
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... De-emphasis Filter The CS4244 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz sample rates not support- ed for 96 kHz or for any settings in Double-speed Mode. The filter response is adjusted to be appropriate for a particular base rate by the if these bits are not set appropriately for the given base rate ...
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... The filter has a single-pole high-pass filter to AC-couple the output signal to the load and a single-pole low-pass filter to attenuate high-frequency energy resulting from the CS4244 DAC’s noise shaping func- tion. ...
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... Alternatively, if the user controls the volume through a knob or slider interface, a volume envelope is sam- pled at a slow, not-necessarily uniform rate (typically 1-20 Hz) and sent to the CS4244. In this case the ramping algorithm detects a short succession of volume changes attempting to track the volume envelope and dynamically adjusts the soft-ramp rate ...
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... See Figure 30 for the soft ramp diagram. On the first volume sample received, the CS4244 only detects the possible beginning of a volume envelope sequence and resets an envelope counter. The volume starts ramping to the new volume setting at a constant rate controlled by the If the envelope counter times out before a new volume sample is received, the next received sample is treated in the same way as the previous sample and the ramp rate is kept constant ...
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... Noise Gate The CS4244 is equipped with a Noise Gate feature that mutes the output if the signal drops below a given bit depth for 8192 samples. While the enabling or disabling of the Noise Gate feature is done for the entire DAC1-4 output path, each of the channels within the path have separate monitoring circuitry that will trig- ger the Noise Gate function independently of the other channels. For instance, if the Noise Gate were en- abled for and one of the channels were to exhibit a pattern of more than 8192 samples of either all “ ...
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... Reset Line The reset line of the CS4244 is used to place the device into a reset condition. In this condition, all of the values of the CS4244 control port are set to their default values. This mode of operation is the lowest power mode of operation for the CS4244 and should be used whenever the device is not operating in order to save power ...
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... Error Reporting and Interrupt Behavior The CS4244 is equipped with a suite of error reporting and protection. The types of errors that are detected, the notification method for these errors, and the steps needed to clear the errors are detailed important to note that the interrupt notification bits for all of the errors are triggered on the edge of the occurrence of the event. They are not level-triggered and therefore do not indicate the presence of an error in real time. This means that, a “ ...
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... PIN[1:0]” bits in the "Interrupt Control" vided that the event is not masked in the mask register. If the CS4244’s interrupt line connected onto a single bus with other devices advisable to use it in the open drain mode of operation other devices are connected to the interrupt line, it may be used in the CMOS mode of operation ...
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... INT pin set to Status Register inactive level bit(s) set to ‘1’ USER: Takes Corrective Action All Status Register bits cleared Are any Yes errors still occurring? No USER: Read Status Registers (see all status bits = ‘0’) CS4244 45 ...
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... ADC2 ADC1 1 1 Reserved Reserved 1 0 DAC1-4 DE Reserved 1 0 Reserved INV. DAC4 1 0 Reserved Reserved MUTE DAC4 1 1 Reserved[1:0] Reserved PDN DAC4 0 1 CS4244 DEV. ID B[3: DEV. ID D[3: DEV. ID F[3: Reserved [3: NUMERIC REV. ID[3: MCLK RATE[2:0] 0 ...
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... Reserved 0 0 MASK MASK Reserved CLK ERR ADC4 OVFL 0 1 MASK Reserved Reserved DAC4 CLIP 1 0 CLK ERR Reserved ADC4 OVFL x x Reserved Reserved DAC4 CLIP x x CS4244 MAX DELAY[2: ...
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... Device I.D. C & D (Address 02h) (Read Only) Device I.D. E & F (Address 03h) (Read Only DEV. ID A[3: DEV. ID C[3: DEV. ID E[3:0] 6.1.1 Device I.D. (Read Only) Device I.D. code for the CS4244. Example:. DEV. ID A[3:0] DEV. ID B[3: 6.2 Revision I.D. (Address 05h) (Read Only AREVID3 AREVID2 AREVID1 6.2.1 Alpha Revision (Read Only) CS4244 Alpha (silicon) revision level ...
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... Reserved 11 Auto Detect (Slave Mode only) 6.3.3 Master Clock Rate Sets the rate at which the master clock is entering the CS4244. Settings are given in “x” multiplied by the incoming sample rate, as MCLK must scale directly with incoming sample rate. MCLK RATE MCLK is: 256xF ...
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... Bits which are wider than the Output Sample Width setting above will be set to zero within the SDOUTx data stream. 6.4.2 Input Sample Width These bits set the width of the samples coming into the CS4244 through the SDINx TDM streams. INPUT SW Sample Width is: 00 ...
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... Setting this bit places the CS4244 in master mode, clearing it places it in slave. MASTER / SLAVE CS4244 is in: 0 Slave Mode 1 Master Mode Note: I²S and Left Justified are the only serial port formats that are available if the CS4244 is placed into Master Mode. 6.6 Serial Port Data Select (Address 09h ADC34 CM ADC12 CM 6 ...
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... Power Down ADCx Powers down the ADCx path. PDN ADCx ADC is: 0 Powered Up 1 Powered Down DS900PP2 ENABLE HPF INV. ADC4 MUTE ADC1 PDN ADC4 CS4244 INV. ADC3 INV. ADC2 INV. ADC1 PDN ADC3 PDN ADC2 PDN ADC1 52 ...
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... Noise Gate Disabled 111 6.9.2 DAC1-4 De-emphasis Enables or disables de-emphasis for the DAC1-4 path. See details. The CS4244 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz base rates not supported for 96 kHz or for any settings in Double-speed Mode. DAC1-4 DE De-emphasis is: 0 Disabled ...
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... Powers down the DACx path. PDN DACx DACx is: 0 Powered Up 1 Powered Down DS900PP2 Reserved MUTE DAC4 for more details regarding the attenuation modes Reserved PDN DAC4 CS4244 MUTE DAC3 MUTE DAC2 MUTE DAC1 PDN DAC3 PDN DAC2 PDN DAC1 54 ...
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... DS900PP2 MIN DELAY[2:0] for more details regarding the operation of the volume control. for more details regarding the operation of the volume control. CS4244 MAX DELAY[2:0] 6. 0.094 dB. Settings are given 64 55 ...
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... In the non-default configuration, the mask bits will not be set automatically. INT MODE Upon the reading of an error out of the interrupt notification bits, the CS4244 will: 0 Automatically set the corresponding mask bit. ...
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... Reserved MASK ADC4 OVFL Power Down ADCx and Power Down DACx (When in slave mode, if the MCLK/F ratio will not be changed.) S CS4244 2 1 MASK MASK MASK ADC3 OVFL ADC2 OVFL ADC1 OVFL bits are set to 1): ratio changes without the de- S Section 4 ...
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... Since the last clearing of the Interrupt Notification Register, a ADCx Overflow Error: 0 Has Not Occurred 1 Has Occurred DS900PP2 MASK Reserved DAC4 CLIP Reserved ADC4 OVFL CS4244 2 1 MASK MASK MASK DAC3 CLIP DAC2 CLIP DAC1 CLIP 2 1 ADC3 OVFL ADC2 OVFL ADC1 OVFL ...
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... A DACx Clip has occurred since the last clearing of the Interrupt Notification register. DACx CLIP Since the last clearing of the Interrupt Notification Register, a DACx Clip Error: 0 Has Not Occurred 1 Has Occurred DS900PP2 Reserved DAC4 CLIP CS4244 DAC3 CLIP DAC2 CLIP DAC1 CLIP 59 ...
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... CS4244 Transition Band 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 Frequency (normalized to Fs) Figure 33. ADC Transition Band Passband Ripple 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (normalized to Fs) Figure 35. ADC Passband Ripple High−Pass Filter Response (Fs = 96kHz ...
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... DAC FILTER PLOTS Figure 38. SSM DAC Stopband Rejection Figure 40. SSM DAC Transition Band (Detail) DS900PP2 CS4244 Figure 39. SSM DAC Transition Band Figure 41. SSM DAC Passband Ripple 61 ...
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... Figure 42. DSM DAC Stopband Rejection Figure 44. DSM DAC Transition Band (Detail) DS900PP2 CS4244 Figure 43. DSM DAC Transition Band Figure 45. DSM DAC Passband Ripple 62 ...
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... Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. DS900PP2 Figure 46. Package Drawing NOM MAX MIN -- 0.0394 -- -- 0.0020 0.00 .0091 .0110 0.18 .1614 .1634 4.05 .1614 .1634 4.04 0.0197 0.30 JEDEC #: MO-220 Controlling Dimension is Millimeters. CS4244 b e PIN #1 CORNER D2 MILLIMETERS NOM MAX -- 1.00 -- 0.05 0.23 0.28 6.00 BSC 4.10 4.15 6.00 BSC 4.10 4.15 .50 BSC 0.40 0.50 NOTE ...
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... Product Description CS4244 4 In/4 Out CODEC CDB4244 CS4244 Evaluation Board DS900PP2 Package Temp Range Container Pb-Free Grade Commercial -40° to +85°C 40-QFN Yes Automotive -40° to +105° CS4244 Order# Rail CS4244-CNZ Tape and CS4244-CNZR Reel Rail CS4244-ENZ Tape and CS4244-ENZR Reel - - CDB4244 64 ...
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... Notification 2 (Address 22h) (Read – Added Section 7. ADC Filter Plots – Changed part number from CS4244-DNZ to CS4244-ENZ in – Removed Over-temperature Warning and Over-temperature Error reporting. – Combined Speed Mode Error and PLL Error into Clocking Error. – Removed DAC1-4 Interpolator Overflow reporting. ...
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... TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² trademark of Philips Semiconductor. DS900PP2 CS4244 66 ...