cs42324 Cirrus Logic, Inc., cs42324 Datasheet - Page 43

• Manufacturer Part Number: cs42324
• Description: 10-in, 6-out, 2 Vrms Audio Codec
• Manufacturer: Cirrus Logic, Inc.

DS721A6
4.6.4
4.7
Interrupts and Overflow
The CS42324 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an
active low open-drain driver (see
tive low open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-
ups with multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an
external pull-up resistor must be placed on the INT pin for proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See
Status (Address 18h) (Read Only)” on page
In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option
of level sensitive or edge sensitive modes within the microcontroller, many different configurations are pos-
sible, depending on the needs of the equipment designer. Reading the Interrupt Status register will clear the
interrupt condtion.
The CS42324 also has a dedicated overflow output. The OVFL pin functions as active low open drain and
has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR
of the ADC Overflow Positive and Negative conditions available in the Interrupt Status register; however,
these conditions do not need to be unmasked for proper operation of the OVFL pin.
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto increment after each byte is written, allowing block reads or writes of successive registers.
5. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring
CDIN
CDOUT
Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
4.6.4.1
CCLK
CS
CS high, and follow the procedure detailed from step 1. If no further reads from other registers are
desired, bring CS high.
ADDRESS
MAP = Memory Address Pointer, 8 bits, MSB first
C H IP
1001111
Map Increment (INCR)
High Impedance
R/W
Figure 22. Software Mode Timing, SPI Mode
M A P
“Operational Control (Address 02h)” on page
MSB
b y te 1
DATA
61. Each source may be masked off through mask register bits.
b y te n
LSB
A D D R E S S
C H IP
1001111
R/W
MSB
47). When configured as ac-
LSB MSB
CS42324
“Interrupt
LSB
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