cs4237b Cirrus Logic, Inc., cs4237b Datasheet - Page 41

• Manufacturer Part Number: cs4237b
• Description: Crystalclear Advanced Audio System With 3d Sound
• Manufacturer: Cirrus Logic, Inc.

ACI
PUR
COR
The SER bit in the Status register (R2) is simply
a logical OR of the COR and PUR bits. This
enables a polling host CPU to detect an error
condition while checking other status bits.
MODE and ID (I12)
Default = 100x1010
ID3-ID0
res
CMS1,0
DS213PP4
D7
1
CMS1
D6
CMS0
Auto-calibrate In-Progress: This bit
indicates the state of calibration.
0 - Calibration not in progress
1 - Calibration is in progress
Playback underrun: This bit is set
when playback data has not arrived
from the host in time to be played.
As a result, if DACZ = 0, the last
valid sample will be sent to the
DACs. This bit is set when an error
occurs and will not clear until the
Status register (R2) is read.
Capture overrun: This bit is set when
the capture data has not been read
by the host before the next sample
arrives. The old sample will not be
overwritten and the new sample will
be ignored. This bit is set when an
error condition occurs and will not
clear until the Status register (R2) is
read.
Codec ID: These four bits indicate the
ID and initial revisions of the codec.
Further revisions are expanded in in-
direct register I25 through the
CS4236 and C1 for newer chips.
These bits are read only.
0001 - Rev B CS4248/CS4231
1010 - All other revisions and parts.
Reserved. Must write 0. Could read
as 0 or 1.
Codec Mode Select bits: Enables the
Extended registers and functions of
the part.
D5
See Registers X25 or C1.
D4
res
D3
ID3
D2
ID2
D1
ID1
D0
ID0
Monitor Loopback Volume (I13)
Default = 000000x0
LBE
res
LBA5-LBA0
Playback Upper Base (I14)
Default = 00000000
PUB7-PUB0
PUB7
LBA5
D7
D7
PUB6
LBA4
D6
D6
PUB5
LBA3
D5
D5
00 - MODE 1
01 - Reserved
10 - MODE 2
11 - MODE 3
ADC data is digitally mixed with data
sent to the DACs. This bit controls
the loopback enable for both chan-
nels regardless of how SLBE in X10
is set.
0 - Loopback disabled
1 - Loopback enabled
Reserved. Must write 0. Could read
as 0 or 1.
determine the attenuation of the loop-
back from ADC to DAC. The least
significant bit represents -1.5 dB,
with 000000 = 0 dB. See Table 6.
LBA5-LBA0 control left and right
channels when SLBE in X10 is
clear. When SLBE = 1, these bits
only control the left channel and
RLBA5- RLBA0 in X10 control the
right.
Playback Upper Base: This register is
the upper byte which represents the
8 most significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
Loopback Enable: When set to 1, the
Loopback Attenuation: These bits
PUB4
LBA2
D4
D4
PUB3
LBA1
D3
D3
PUB2
LBA0
D2
D2
PUB1
CS4237B
D1
D1
res
PUB0
LBE
D0
D0
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