cs4924 Cirrus Logic, Inc., cs4924 Datasheet - Page 10

• Manufacturer Part Number: cs4924
• Description: Multi-channel Digital Audio Decoders Logic
• Manufacturer: Cirrus Logic, Inc.

SWITCHING CHARACTERISTICS—MOTOROLA
(T
Notes: 3. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can
10
Address setup before CS and DS low
Address hold time after CS and DS low
Delay between DS then CS low or CS then DS low
Data valid after CS and DS low with R/W high
CS and DS low for read
Data hold time after CS or DS high after read
Data high-Z after CS or DS high low after read
CS or DS high to CS and DS low for next read
CS or DS high to CS and DS low for next write
Delay between DS then CS low or CS then DS low
Data setup before CS or DS high
CS and DS low for write
R/W setup before CS or DS low
R/W hold time after CS or DS high
Data hold after CS or DS high
CS or DS high to CS and DS low with R/W high for next read
CS or DS high to CS and DS low for next write
A
= 25 C; VA, VD = 3.3 V 5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
4. This specification is characterized but not production tested.
be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/3 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLK == 100ns
DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see
CS4923/4/5/6/7/8/9 Hardware Users Guide for more information)
Parameter
(Note 3)
(Note 4)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
mrwhld
mrwsu
mwpw
mrdtw
mcdw
mdhw
mwtrd
mrpw
mdsu
mcdr
mdhr
mdis
mwd
mah
mdd
mas
mrd
®
HOST MODE
L
2*DCLK + 10
2*DCLK + 10
2*DCLK + 10
2*DCLK + 10
DCLK + 10
DCLK + 10
= 20 pF)
Min
20
5
5
0
5
0
5
5
5
-
-
CS4923/4/5/6/7/8/9
Max
20
15
-
-
-
-
-
-
-
-
-
-
-
-
-
DS262F2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns