ltc2258cuj-12 Linear Technology Corporation, ltc2258cuj-12 Datasheet - Page 14

• Manufacturer Part Number: ltc2258cuj-12
• Description: 12-bit, 65/40/2 5msps Ultralow Power 1.8v Adcs
• Manufacturer: Linear Technology Corporation

PIN FUNCTIONS
LTC2258-12
LTC2257-12/LTC2256-12
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
A
A
GND (Pin 3): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
PAR/SER (Pin 8): Programming Mode Selection Pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to V
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the V
logic signal.
14
TYPICAL PERFORMANCE CHARACTERISTICS
IN
IN
25
20
15
10
+
–
(Pin 1): Positive Differential Analog Input.
(Pin 2): Negative Differential Analog Input.
LTC2256-12: I
5MHz Sine Wave Input, –1dB
0
LVDS OUTPUTS
SAMPLE RATE (Msps)
CMOS OUTPUTS
10
VDD
DD
vs Sample Rate,
of the part and not be driven by a
20
226112 G53
DD
45
40
35
30
25
20
15
10
to enable the
5
0
0
LTC2256-12: IO
5MHz Sine Wave Input, –1dB, 5pF
on Each Data Output
SAMPLE RATE (Msps)
10
1.8V CMOS
1.75mA LVDS
VDD
3.5mA LVDS
V
to ground with 0.1μF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
ENC
rising edge.
ENC
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = V
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = V
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double
vs Sample Rate,
DD
+
–
(Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
1.2V CMOS
(Pin 11): Encode Input. Conversion starts on the
(Pin 12): Encode Complement Input. Conversion
20
225812 G54
DD
), CS controls the clock duty cycle
72
71
70
69
68
67
66
0.6
LTC2256-12: SNR vs SENSE,
f
IN
= 5MHz, –1dB
0.7
0.8
DD
SENSE PIN (V)
0.9
), SCK controls the
1.0
1.1
1.2
225812 G55
225812p
1.3