ltc2258cuj-12 Linear Technology Corporation, ltc2258cuj-12 Datasheet - Page 24

• Manufacturer Part Number: ltc2258cuj-12
• Description: 12-bit, 65/40/2 5msps Ultralow Power 1.8v Adcs
• Manufacturer: Linear Technology Corporation

LTC2258-12
LTC2257-12/LTC2256-12
APPLICATIONS INFORMATION
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit
polarity mode is independent of the digital output random-
izer—either, both or neither function can be on at the same
time. When alternate bit polarity mode is on, the data
format is offset binary and the 2’s complement control bit
has no effect. The alternate bit polarity mode is enabled
by serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D11-D0) to known values:
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs including
OF and CLKOUT are disabled. The high impedance disabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down, resulting in 0.5mW power consumption. Sleep mode
is enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on V
24
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 1010101010101
to 0101010101010 on alternating samples
REF
,
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
mode requires at least 100 clock cycles. If the application
demands very accurate DC settling then an additional
50μs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2258-12 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more fl exibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V
inputs that set certain operating modes. These pins can
be tied to V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = V
PIN
CS
SCK
SDI
DESCRIPTION
Clock Duty Cycle Stabilizer Control Bit
Digital Output Mode Control Bit
Power Down Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
0 = Full-Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
0 = Normal Operation
1 = Sleep Mode
DD
(3.5mA LVDS Current, Internal Termination Off)
DD
. The CS, SCK and SDI pins are binary logic
or ground, or driven by 1.8V, 2.5V or 3.3V
225812p
DD
)