ltc2258cuj-12 Linear Technology Corporation, ltc2258cuj-12 Datasheet - Page 15

• Manufacturer Part Number: ltc2258cuj-12
• Description: 12-bit, 65/40/2 5msps Ultralow Power 1.8v Adcs
• Manufacturer: Linear Technology Corporation

PIN FUNCTIONS
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
V
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessary and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = V
and should not be connected.
OGND (Pin 25): Output Driver Ground.
OV
with a 0.1μF ceramic capacitor.
V
Equal to V
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
V
with a 1μF ceramic capacitor, nominally 1.25V.
SENSE (Pin 39): Reference Programming Pin. Connecting
SENSE to V
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • V
DD
CM
REF
DD
), SDI can be used to power down the part. When SDI
(Pin 38): Reference Voltage Output. Bypass to ground
(Pin 37): Common Mode Bias Output, Nominally
(Pin 26): Output Driver Supply. Bypass to ground
DD
DD
/2. V
selects the internal reference and a ±1V input
CM
should be used to bias the common
SENSE
.
DD
), SDO is not used
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OV
D0 to D11 (Pins 19-24, 29-34): Digital Outputs. D11 is
the MSB.
CLKOUT
CLKOUT
normally transition at the same time as the falling edge
of CLKOUT
relative to the digital outputs by programming the mode
control registers.
DNC (Pins 17, 18, 35): Do not connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overfl ow or underfl ow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OV
D0_1 to D10_11 (Pins 20, 22, 24, 30, 32, 34): Double Data
Rate Digital Outputs. Two data bits are multiplexed onto
each output pin. The even data bits (D0, D2, D4, D6, D8,
D10) appear when CLKOUT
D3, D5, D7, D9, D11) appear when CLKOUT
CLKOUT
CLKOUT
normally transition at the same time as the falling and ris-
ing edges of CLKOUT
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 18, 19, 21, 23, 29, 31, 33, 35): Do not
connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overfl ow or underfl ow has occurred.
DD
DD
)
)
LTC2257-12/LTC2256-12
–
+
–
+
(Pin 28): Data Output Clock. The digital outputs
(Pin 28): Data Output Clock. The digital outputs
(Pin 27): Inverted version of CLKOUT
(Pin 27): Inverted version of CLKOUT
+
. The phase of CLKOUT
+
. The phase of CLKOUT
+
is low. The odd data bits (D1,
LTC2258-12
+
can also be delayed
+
is high.
+
+
+
can also
.
.
15
225812p