nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 43

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 6 8-Bit Arithmetic
Timing
Addressing Mode
Timing
Addressing Mode
12 7 16-Bit Arithmetic
ADD
Add the contents of the 16-bit register rp or pp to the con-
tents of the 16-bit register ss
ss
ss
Timing
Addressing Mode
Timing
Addressing Mode
ADC
The contents of the 16-bit register pp are added with the
carry bit to the HL register
HL
7 6
1 1 N
0 0
7
0
7
0
7
1
0
6
1
0
6
0
6
0
ss
or
ss
N
1
5
1
HL
5
5
ss pp
5
HL pp
X
X
rp
pp
a
a
a
4
1
4
4 3 2 1 0
1 1 1 0 1
1 0 1 0 1
rp
pp
4
1
d
pp
3
0
3
1
3
1
1
P V N A
a
H Set if carry from bit 11
N Reset
S N A
Z N A
C Set if carry from bit 15
2
1
2
0
2
1
0
CY
M cycles
T states
Source
Destination
M cycles
T states
Source
Destination
1
0
1
0
1
0
0
H Set according to carry out of bit
S Set if result is negative
Z Set if result is zero
0
1
0
1
M cycles
T states
Source
Destination
dexed
M cycles
T states
Source
Destination
0
1
1
11
ADD HL rp
DEC (IX
DEC (IY
Register
Register
DEC (HL)
ADD IX pp (for N
ADD IY pp (for N
11 (4 4 3)
15 (4 4 4 3)
(Continued)
3
4
Register
Register
Register Indexed
Indexed
11 (4 4 3)
23 (4 4 3 5 4 3)
3
a
6
a
Indexed
d) (for N
d) (for N
Register In-
X
X
X
X
e
e
e
e
0)
1)
0)
1)
43
Timing
Addressing Mode
SBC
Subtract with carry the contents of the 16-bit pp register
from the 16-bit HL register
HL
Timing
Addressing Mode
INC
Increment the contents of the 16-bit register rr
rr
Timing
Addressing Mode
Timing
Addressing Mode
7
1
0
7
1
0
7
1
0
7
0
6
1
0
6
1
1
6
1
1
6
0
rr
rr
N
HL
5
5
1
5
1
HL pp
a
5
1
X
pp
pp
rp
1
b
4
4
0
4
0
4
1
0
pp
3
0
3
1
1
3
1
0
3
1
0
b
2
0
2
1
0
2
1
0
2
1
0
CY
P V Set if result exceeds 16-bit 2’s
P V Set if result exceeds 16-bit 2’s
1
1
1
0
1
1
0
1
1
0
1
N Reset
C Set if carry out of bit 15
H Set according to borrow from
N Set
C Set according to borrow condi-
S Set if result is negative
Z Set if result is zero
complement range
M cycles
T states
Source
Destination
bit 12
complement range
tion
M cycles
T states
Source
Destination
No flags affected
0
1
M cycles
T states
Register
M cycles
T states
Register
0
1
0
0
1
0
0
1
1
INC BC
INC DE
INC HL
INC SP
INC IX (for N
INC IY (for N
Register
Register
15 (4 4 4 3)
15 (4 4 4 3)
6
10 (4 6)
4
4
1
2
Register
Register
X
X
e
e
0)
1)