nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 54

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 12 Input Output
INDR
Data is input from the I O device at address (C) to memory
location (HL) then the HL memory pointer is byte counter B
are decremented The cycle is repeated until B
(Note that B is tested for zero after it is decremented By
loading B initially with zero 256 data transfers will take
place )
(HL)
HL
B
Repeat until B
Timing
Addressing Mode
(Note that after each data transfer cycle interrupts may be
recognized and two refresh cycles are performed )
OTDR
Data is output from memory location (HL) to the I O device
at port address (C) then the HL memory pointer and byte
counter B are decremented The cycle is repeated until B
0
(Note that B is tested for zero after it is decremented By
loading B initially with zero 256 data transfers will take
place )
(C)
HL
B
Repeat until B
Timing
Addressing Mode
(Note that after each data transfer cycle the NSC800 will
accept interrupts and perform two refresh cycles )
7
1
1
7
1
1
6
1
0
6
1
0
B
B
5
1
1
5
1
1
HL
HL
(HL)
b
b
(C)
For B
For B
For B
For B
4
0
1
4
0
1
b
1
b
1
1
e
1
e
3
1
0
3
1
1
i
e
i
e
0
0
2
1
0
2
1
0
0
0
0
0
P V Undefined
P V Undefined
1
0
1
1
0
1
H Undefined
N Set
C N A
H Undefined
N Set
C N A
S Undefined
Z Set
S Undefined
Z Set
0
1
0
0
1
1
M cycles
T states
M cycles
T states
Implied Source
direct
Destination
M cycles
T states
M cycles
T states
Implied Source
direct
Destination
(Continued)
21 (4 5 3 4 5)
16 (4 5 3 4)
21 (4 5 3 4 5)
16 (4 5 3 4)
5
4
5
4
Register Indirect
Register Indirect
Register In-
Register In-
e
0
e
54
12 13 CPU Control
NOP
The CPU performs no operation
Timing
Addressing Mode
HALT
The CPU halts execution of the program Dummy op-code
fetches are performed from the next memory location to
keep the refresh circuits active until the CPU is interrupted
or reset from the halted state
Timing
Addressing Mode
DI
Disable system level interrupts
IFF
IFF
Timing
Addressing Mode
EI
The system level interrupts are enabled During execution of
this instruction and the next one the maskable interrupts
will be disabled
IFF
IFF
Timing
Addressing Mode
IM
The CPU is placed in interrupt mode 0
Timing
Addressing Mode
7
0
7
0
7
1
7
1
7
1
0
1
2
1
2
6
0
6
1
6
1
6
1
6
1
1
0
5
0
5
1
5
1
5
1
5
1
0
0
0
1
1
4
0
4
1
4
1
4
1
4
0
0
3
0
3
0
3
0
3
1
3
1
0
2
0
2
1
2
0
2
0
2
1
1
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
1
0
1
0
No flags affected
M cycles
T states
N A
No flags affected
M cycles
T states
N A
No flags affected
M cycles
T states
N A
No flags affected
M cycles
T states
N A
No flags affected
M cycles
T states
N A
4
4
4
4
8 (4 4)
1
1
1
1
2