nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 51

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 11 Memory Block Moves and Searches
Timing
Addressing Mode
REPEAT OPERATIONS
LDIR
Move data from memory location (HL) to memory location
(DE) increment memory pointers decrement byte counter
BC and repeat until BC
(DE)
DE
HL
BC
Repeat until
Timing
Addressing Mode
(Note that each repeat is accomplished by a decrement of
the BC so that refresh etc continues for each cycle )
LDDR
Move data from memory location (HL) to memory location
(DE) decrement memory pointers and byte counter BC and
repeat until BC
(DE)
DE
HL
BC
Repeat until
Timing
Addressing Mode
(Note that each repeat is accomplished by a decrement of
the BC so that refresh etc continues for each cycle )
7
1
1
7
1
1
7
1
1
BC
BC
6
1
0
6
1
0
6
1
0
e
e
HL
HL
5
1
1
DE
BC
5
1
1
DE
BC
5
1
1
0
0
(HL)
(HL)
For BC
For BC
For BC
For BC
a
b
4
0
0
b
4
0
1
b
b
4
0
1
a
1
1
1
1
1
1
e
3
1
1
3
1
0
3
1
1
0
e
e
i
i
2
1
0
2
1
0
2
1
0
0 M cycles
0 M cycles
0 M cycles
0 M cycles
P V Reset
P V Reset
T states
T states
T states
T states
Register Indirect
Register Indirect
1
0
0
1
0
0
1
0
0
e
H Reset
N Reset
H Reset
N Reset
S N A
C N A
S N A
C N A
Z N A
Z N A
0
M cycles
T states
Register Indirect
0
1
1
0
1
0
0
1
0
21 (4 4 3 5 5)
16 (4 4 3 5)
21 (4 4 3 5 5)
16 (4 4 3 5)
5
4
5
4
16 (4 4 3 5)
4
51
CPIR
Compare data in memory location (HL) to the Accumulator
increment the memory decrement the byte counter BC and
repeat until BC
A
HL
BC
Repeat until BC
Timing
Addressing Mode
(Note that each repeat is accomplished by a decrement of
the PC so that refresh etc continues for each cycle )
CPDR
Compare data in memory location (HL) to the contents of
the Accumulator decrement the memory pointer and byte
counter BC and repeat until BC
the Accumulator
A
HL
BC
Repeat until BC
Timing
Addressing Mode
(Note that each repeat is accomplished by a decrement of
the BC so that refresh etc continues for each cycle )
7
1
1
7
1
1
or A
or A
b
b
(Continued)
6
1
0
6
1
0
(HL)
(HL)
e
e
HL
HL
BC
5
1
1
BC
5
1
1
(HL)
(HL)
For BC
For BC
For BC
For BC
a
b
b
4
0
1
b
4
0
1
1
1
1
1
e
3
1
0
3
1
1
e
e
0 or (HL) equals A
i
e
i
e
0
0
2
1
0
2
1
0
0
0
0
0
P V Set if BC
P V Set if BC
1
0
0
1
0
0
H Set according to borrow from
N Set
C N A
H Set according to borrow from
N Set
C N A
S Set if sign of subtraction per-
Z Set if A
S Set if sign of subtraction per-
Z Set according to equality of A
formed for comparison is nega-
tive
bit 4
reset
M cycles
T states
M cycles
T states
Register Indirect
formed for comparison is nega-
tive
and (HL) set if true
bit 4
reset
M cycles
T states
M cycles
T states
Register Indirect
0
1
1
0
1
1
e
e
0 or until (HL) equals
b
b
(HL) otherwise reset
21 (4 4 3 5 5)
16 (4 4 3 5)
21 (4 4 3 5 5)
16 (4 4 3 5)
5
4
5
4
1
1
i
i
0 otherwise
0 otherwise