nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 55

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 13 CPU Control
IM
The CPU is placed in interrupt mode 1
Timing
Addressing Mode
IM
The CPU is placed in interrupt mode 2
Timing
Addressing Mode
12 14 Program Control
JUMPS
JP
Unconditional jump to program location nn
PC
Timing
Addressing Mode
JP
Unconditional jump to program location pointed to by regis-
ter ss
PC
Timing
Addressing Mode
7
1
0
7
1
0
7
1
7
1
1
1
6
1
1
1
1
6
6
6
n (high-order byte)
n (low-order byte)
1
2
nn
(ss)
nn
ss
5
1
0
5
1
0
5
0
5
1
4
0
1
4
0
1
4
0
4
0
3
1
0
3
1
1
3
0
3
1
2
1
1
2
1
1
2
0
2
0
1
0
1
1
0
1
1
1
1
0
0
1
0
0
1
0
0
1
0
1
No flags affected
M cycles
T states
N A
No flags affected
M cycles
T states
N A
No flags affected
M cycles
T states
Direct
No flags affected
M cycles
T states
Register Indirect
(Continued)
JP (HL)
8 (4 4)
8 (4 4)
10 (4 3 3)
4
2
2
3
1
55
Timing
Addressing Mode
JP
Conditionally jump to program location nn based on testable
flag states
If cc true
PC
otherwise continue
Timing
Addressing Mode
JR
Unconditional jump to program location calculated with re-
spect to the program counter and the displacement d
PC
Timing
Addressing Mode
JR
Conditionally jump to program location calculated with re-
spect to the program counter and the displacement d
based on limited testable flag states
If kk true
PC
otherwise continue
Timing
Addressing Mode
7 6
1 1 N
1 1
7
1
7
0
7
0
6
1
6
0
6
0
n (high-order byte)
n (low-order byte)
cc nn
d
kk d
5
nn
PC
PC
5
0
5
1
5
1
X
if kk met
(true)
if kk not met
(not true)
cc
d
d
a
a
4
1
4
4
4 3 2 1 0
1 1 1 0 1
0 1 0 0 1
b
kk
b
d
d
3
1
3
2
2
3
2
0
2
0
2
0
1
0
1
0
1
1
0
0
0
0
0
0
M cycles
T states
Register Indirect
No flags affected
M cycles
T states
Direct
No flags affected
M cycles
T states
PC Relative
No flags affected
M cycles
T states
M cycles
T states
PC Relative
JP (IX) (for N
JP (IY) (for N
8 (4 4)
10 (4 3 3)
12 (4 3 5)
12 (4 3 5)
7 (4 3)
2
3
3
3
2
X
X
e
e
0)
1)