ltc2484 Linear Technology Corporation, ltc2484 Datasheet - Page 16

• Manufacturer Part Number: ltc2484
• Description: 24-bit Delta Sigma Adc With Easy Drive Input Current Cancellation
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC2484
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 2.
Table 2. LTC2484 Status Bits
INPUT RANGE
V
0V ≤ V
–0.5 • V
V
Bits 28-5 are the 24-bit conversion result MSB first.
Bits 4–0 are sub LSBs below the 24-bit level. Bits 4–0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK) (see Figure 2). Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
16
IN
IN
≥ 0.5 • V
< – 0.5 • V
IN
REF
< 0.5 • V
Table 3. LTC2484 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
V
V
FS** – 1LSB
0.5 • FS**
0.5 • FS** – 1LSB
0
–1LSB
– 0.5 • FS**
– 0.5 • FS** – 1LSB
– FS**
V
*The differential input voltage V
≤ V
IN
IN
IN
REF
* ≥ FS**
* < –FS**
REF
*
IN
REF
< 0V
U
U
BIT 31 BIT 30 BIT 29 BIT 28
EOC
IN
0
0
0
0
= IN
W
BIT 31
EOC
0
0
0
0
0
0
0
0
0
0
+
DMY
– IN
0
0
0
0
–
. **The full-scale voltage FS = 0.5 • V
BIT 30
DMY
SIG
0
0
0
0
0
0
0
0
0
0
1
1
0
0
U
MSB
BIT 29
SIG
1
0
1
0
1
1
1
1
1
0
0
0
0
0
BIT 28
MSB
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes in real time
from HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 3 summarizes
the output data format.
As long as the voltage on the IN
within the – 0.3V to (V
operating range, a conversion result is generated
for any differential input voltage V
–FS = –0.5 • V
voltages greater than +FS, the conversion result is clamped
to the value corresponding to the +FS + 1LSB. For
differential input voltages below –FS, the conversion re-
sult is clamped to the value corresponding to –FS – 1LSB.
1
0
0
0
0
1
1
1
1
0
BIT 27
0
1
1
0
0
1
1
0
0
1
REF
.
REF
BIT 26
to +FS = 0.5 • V
0
1
0
1
0
1
0
1
0
1
BIT 25
CC
0
1
0
1
0
1
0
1
0
1
+ 0.3V) absolute maximum
+
and IN
REF
…
…
…
…
…
…
…
…
…
…
…
. For differential input
–
pins is maintained
BIT 0
0
1
0
1
0
1
0
1
0
1
IN
from
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