ltc2484 Linear Technology Corporation, ltc2484 Datasheet - Page 25

• Manufacturer Part Number: ltc2484
• Description: 24-bit Delta Sigma Adc With Easy Drive Input Current Cancellation
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
then immediately begins outputting data. The data input/
output cycle begins on the first rising edge of SCK and
ends after the 32nd rising edge. The input data is then
shifted in via the SDI pin on the rising edge of SCK
(including the first rising edge) and the output data is
shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2484 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
24-bit accuracy capability of this part, some simple pre-
cautions are required.
(INTERNAL)
SDO
SDI*
SCK
CS
CONVERSION
DON’T CARE
U
BIT 23
EOC
EN
U
BIT 22
GS2
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
W
BIT 21
SIG
GS1
BIT 20
MSB
GS0
U
0.1V TO V
REFERENCE
VOLTAGE
ANALOG
BIT 19
INPUT
1µF
2.7V TO 5.5V
IM
CC
2
3
4
5
BIT 18
V
V
IN
IN
CC
REF
FA
+
–
LTC2484
Digital Signal Levels
The LTC2484’s digital interface is easy to use. Its digital
inputs (SDI, F
operation) accept standard CMOS logic levels and the in-
ternal hysteresis receivers can tolerate edge transition times
as slow as 100µs. However, some considerations are re-
quired to take advantage of the exceptional accuracy and
low supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, F
and SCK in External SCK mode of operation) is within
this range, the power supply current may increase even
if the signal in question is at a valid logic level. For
micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [V
V
DATA OUTPUT
OH
BIT 17
CC
SDO
GND
SCK
SDI
CS
F
O
FB
> (V
– 0.5V), the CMOS input receiver draws additional
7
6
8
10
9
1
BIT 16
CC
INT/EXT CLOCK
SPD
3-WIRE
SPI INTERFACE
– 0.4V)].
O
, CS and SCK in External SCK mode of
V
CC
BIT 4
DON’T CARE
10k
LSB
BIT 0
IM
LTC2484
IL
< 0.4V and
CONVERSION
25
O
, CS
2484fa
2484 F10