ltc2484 Linear Technology Corporation, ltc2484 Datasheet - Page 28

• Manufacturer Part Number: ltc2484
• Description: 24-bit Delta Sigma Adc With Easy Drive Input Current Cancellation
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC2484
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
28
V
V
INCM
INCM
Figure 13. +FS Error vs R
Figure 14. –FS Error vs R
–20
–40
–80
–20
–40
–80
–60
–60
+ 0.5V
– 0.5V
80
60
40
20
Figure 12. An RC Network at IN
80
60
40
20
0
0
1
1
V
V
V
V
F
T
V
V
V
V
F
T
O
A
O
CC
REF
IN
IN
IN
IN
CC
REF
IN
IN
A
= GND
= 25°C
= GND
= 25°C
+
–
+
–
= 5V
= 5V
= 1.25V
= 3.75V
= 3.75V
= 1.25V
= 5V
= 5V
10
10
U
R
R
SOURCE
SOURCE
C
R
100
100
R
IN
SOURCE
SOURCE
C
U
= 1nF, 0.1µF, 1µF
IN
= 1nF, 0.1µF, 1µF
C
C
(Ω)
(Ω)
C
1k
1k
IN
IN
C
SOURCE
SOURCE
IN
IN
= 100pF
C
= 100pF
IN
C
W
= 0pF
IN
10k
10k
C
≅ 20pF
C
≅ 20pF
= 0pF
at IN
at IN
PAR
PAR
+
and IN
2484 F14
2484 F13
100k
+
+
100k
or IN
or IN
IN
IN
LTC2484
+
–
–
U
–
–
2484 F12
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
the common mode input current effects are rejected by the
large CMRR of the LTC2484 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1kΩ source resistances lead
to gain worst-case gain errors on the order of 15ppm (for
1V differences in reference and input common mode
voltage). Table 6 summarizes the effects of mismatched
source impedance and differences in reference/input com-
mon mode voltages.
Table 6. Suggested Input Configuration for LTC2484
Constant
V
Varying
V
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN
IN
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and 10µV maximum offset voltage.
IN(CM)
IN(CM)
–
, the expected drift of the dynamic current and offset
– V
– V
REF(CM)
REF(CM)
BALANCED INPUT
RESISTANCES
C
IN
Large Source Resistance Source Resistance.
with Negligible Error
C
and IN
Source Resistance with
Negligible Error
IN
IN
+
> 1nF at Both
> 1nF at Both IN
and IN
–
. Can Take Large
–
. Can Take
+
UNBALANCED INPUT
RESISTANCES
C
and IN
Unbalanced Resistance
Results in an Offset
Which Can be Calibrated
Minimize IN
Capacitors and Avoid
Large Source Impedance
(< 5k Recommended)
IN
> 1nF at Both IN
–
. Can Take Large
+
and IN
+
+
–
2484fa
and