ltc2484 Linear Technology Corporation, ltc2484 Datasheet - Page 24

• Manufacturer Part Number: ltc2484
• Description: 24-bit Delta Sigma Adc With Easy Drive Input Current Cancellation
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC2484
Whenever SCK is LOW, the LTC2484’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2484’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH once
the external driver goes Hi-Z. On the next CS falling edge,
the device will remain in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
24
(INTERNAL)
SDO
SCK
SLEEP
SDI
CS
Hi-Z
> t
OUTPUT
DATA
EOCtest
BIT 0
EOC
U
CONVERSION
Hi-Z
DON’T CARE
TEST EOC
U
EOCtest
Hi-Z
SLEEP
(OPTIONAL)
TEST EOC
), the internal pull-up is
SLEEP
Figure 9. Internal Serial Clock, Reduce Data Output Length
Hi-Z
W
<t
EOCtest
BIT 31
EOC
EN
BIT 30
U
REFERENCE
0.1V TO V
VOLTAGE
ANALOG
DON’T CARE
BIT 29
INPUT
1µF
SIG
2.7V TO 5.5V
CC
2
3
4
5
BIT 28
MSB
V
V
IN
IN
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal, see Figure 10. CS may be perma-
nently tied to ground, simplifying the user interface or
transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
CC
REF
+
–
LTC2484
GND
BIT 27
SDO
SCK
SDI
CS
F
O
DATA OUTPUT
IM
7
8
10
1
9
6
BIT 26
FOA
INT/EXT CLOCK
4-WIRE
SPI INTERFACE
BIT 25
FOB
V
CC
CC
BIT 24
10k
SPD
exceeds 2V. An internal weak
BIT 8
DON’T CARE
CONVERSION
Hi-Z
TEST EOC
2484fa
2484 F09