mbm29dl324te90tr Meet Spansion Inc., mbm29dl324te90tr Datasheet - Page 49

• Manufacturer Part Number: mbm29dl324te90tr
• Description: 32 M 4 M ? 8/2 M ? 16 Bit Dual Operation Flash Memory
• Manufacturer: Meet Spansion Inc.

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
for Data Polling (DQ
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling also works as a flag to indicate whether the device is in erase-suspended
mode. DQ
suspended mode, indicate the sector adress of sector being erased. Data Polling must be performed at sector
address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid.
If a program address falls within a protected sector, Data Polling on DQ
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
Once the Embedded Algorithm operation is close to being completed, the MBM29DL32XTE/BE data pins (DQ
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ
Depending on when the system samples the DQ
has completed the Embedded Algorithm operation and DQ
may be still invalid. The valid data on DQ
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See “Hardware Sequence Flags” in “■ COMMAND DEFINITIONS”.)
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the
Data Polling timing specifications and diagrams.
• DQ
Toggle Bit I
The MBM29DL32XTE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 μs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
cause the DQ
The system can use DQ
is actively erasing (that is, the Embedded Erase Algorithm is in progress) , DQ
the Erase Suspend mode, DQ
DQ
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See “Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the
Toggle Bit I timing specifications and diagrams.
6
to toggle.
6
7
goes from “0” to “1” during erase-suspended mode. Notice that to determine DQ
6
to toggle.
7
) is shown in “Data Polling Algorithm” in “■ FLOW CHART”.
6
6
will stop toggling and valid data will be read on the next successive attempts. During
to determine whether a sector is actively erasing or is erase-suspended. When a bank
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm
6
stops toggling. Successive read cycles during the erase-suspend-program cause
7
at one instant of time and then that byte’s valid data at the next instant of time.
Retired Product DS05-20881-8E_July 20, 2007
7
0
is active for approximately 400 μs, then the bank returns to read mode.
to DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
7
7
output, it may read the status or valid data. Even if the device
will be read on the successive read attempts.
MBM29DL32XTE/BE
7
has a valid data, the data outputs on DQ
7
is active for approximately 1 μs, then
6
toggles. When a bank enters
7
output. The flowchart
7
entering erase-
0
to DQ
80 / 90
7
)
6
49